ATMEGA644PV-10MQ Atmel, ATMEGA644PV-10MQ Datasheet - Page 172
![MCU AVR 64K FLASH 10MHZ 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA644PV-10MQ
Manufacturer Part Number
ATMEGA644PV-10MQ
Description
MCU AVR 64K FLASH 10MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644PV-10MQ
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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16.4
8011O–AVR–07/10
Clock Generation
Figure 16-1. USART Block Diagram
Note:
The dashed boxes in the block diagram separate the three main parts of the USART (listed from
the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.
The Clock Generation logic consists of synchronization logic for external clock input used by
synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is
only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a
serial Shift Register, Parity Generator and Control logic for handling different serial frame for-
mats. The write buffer allows a continuous transfer of data without any delay between frames.
The Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level
receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USARTn supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART
Control and Status Register C (UCSRnC) selects between asynchronous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
1. See
placement.
Figure 1-1 on page 2
UCSRA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDR (Transmit)
UDR (Receive)
and
UBRR[H:L]
(1)
”Alternate Port Functions” on page 78
UCSRB
ATmega164P/324P/644P
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
CHECKER
PARITY
CLOCK
PARITY
DATA
OSC
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
PIN
TX
RX
Receiver
UCSRC
for USART pin
XCK
RxD
TxD
172
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