DSPIC33FJ64MC706-I/PT Microchip Technology, DSPIC33FJ64MC706-I/PT Datasheet - Page 144

• Manufacturer Part Number: DSPIC33FJ64MC706-I/PT
• Description: IC DSPIC MCU/DSP 64K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64MC706-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Core Frequency: 40MHz
• Embedded Interface Type: ECAN, I2C, SPI, UART
• No. Of I/o's: 53
• Flash Memory Size: 64KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 32-chx10-bit|32-chx12-bit
• Number Of Timers: 9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33F
REGISTER 7-3:
REGISTER 7-4:
DS70165E-page 142
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
Note 1:
R/W-0
R/W-0
R/W-0
R/W-0
A read of this address register will return the current contents of the DMA RAM Address register, not the
contents written to STA<15:0>. If the channel is enabled (i.e., active), writes to this register may result in
unpredictable behavior of the DMA channel and should be avoided.
A read of this address register will return the current contents of the DMA RAM Address register, not the
contents written to STB<15:0>. If the channel is enabled (i.e., active), writes to this register may result in
unpredictable behavior of the DMA channel and should be avoided.
STA<15:0>: Primary DMA RAM Start Address bits (source or destination)
STB<15:0>: Secondary DMA RAM Start Address bits (source or destination)
R/W-0
R/W-0
R/W-0
R/W-0
DMAxSTA: DMA CHANNEL x RAM START ADDRESS REGISTER A
DMAxSTB: DMA CHANNEL x RAM START ADDRESS REGISTER B
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Preliminary
STA<15:8>
STB<15:8>
STA<7:0>
STB<7:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
© 2007 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
(1)
(1)
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0
bit 8
bit 0