DSPIC33FJ32MC204-I/PT Microchip Technology, DSPIC33FJ32MC204-I/PT Datasheet - Page 189
![IC DSPIC MCU/DSP 32K 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
DSPIC33FJ32MC204-I/PT
Manufacturer Part Number
DSPIC33FJ32MC204-I/PT
Description
IC DSPIC MCU/DSP 32K 44TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(320 pages)
2.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
3.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
4.DSPIC33FJ32MC204-IPT.pdf
(304 pages)
Specifications of DSPIC33FJ32MC204-I/PT
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
44-TQFP, 44-VQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330011, DM330021, MA330017
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ32MC204-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC202-IMM PDF datasheet #2
- DSPIC33FJ32MC202-IMM PDF datasheet #3
- DSPIC33FJ32MC204-IPT PDF datasheet #4
- Current page: 189 of 304
- Download datasheet (3Mb)
REGISTER 18-2:
2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
ACKSTAT
R/C-0 HS
R-0 HSC
IWCOL
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
ACKSTAT: Acknowledge Status bit
(when operating as I
1 = NACK received from slave
0 = ACK received from slave
Hardware set or clear at end of slave Acknowledge.
TRSTAT: Transmit Status bit (when operating as I
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.
Unimplemented: Read as ‘0’
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware set at detection of bus collision.
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware set when address matches general call address. Hardware clear at Stop detection.
ADD10: 10-bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
IWCOL: Write Collision Detect bit
1 = An attempt to write the I2CxTRN register failed because the I
0 = No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
D_A: Data/Address bit (when operating as I
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of slave byte.
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
R/C-0 HS
R-0 HSC
TRSTAT
I2COV
I2CxSTAT: I2Cx STATUS REGISTER
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
R-0 HSC
D_A
U-0
—
2
C master, applicable to master transmit operation)
R/C-0 HSC
U-0
—
Preliminary
P
HS = Set in hardware
‘0’ = Bit is cleared
R/C-0 HSC
2
C slave)
U-0
—
S
2
C master, applicable to master transmit operation)
R/C-0 HS
R-0 HSC
R_W
BCL
2
C module is busy
HSC = Hardware set/cleared
x = Bit is unknown
R-0 HSC
GCSTAT
R-0 HSC
RBF
DS70283G-page 189
R-0 HSC
R-0 HSC
ADD10
TBF
bit 8
bit 0
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