PIC18F27J53-I/ML Microchip Technology, PIC18F27J53-I/ML Datasheet - Page 2
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PIC18F27J53-I/ML
Manufacturer Part Number
PIC18F27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18F27J53-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIC18F47J53 FAMILY
TABLE 2:
DS80506C-page 2
CTMU
Oscillator
Configurations
ADC
EUSART
MSSP
MSSP
EUSART
Note 1:
Module
Only those issues indicated in the last column apply to the current silicon revision.
SILICON ISSUE SUMMARY
Constant
Current
Source
PLL
A/D
Receive
Baud Rate
I
Mode
I
Reception
Enable/
Disable
2
2
C™
C Slave
Feature
Number
Item
1.
2.
3.
4.
5.
6.
7.
Band gap must be manually enabled before using the
CTMU.
PLL can not be enabled unless the 8 or 4 MHz INTOSC
option is set.
ANx pin may output a pull-up pulse during acquisition.
Receive and transmit baud rates differ due to different clock
sources.
If a Stop condition occurs in the middle of an address or
data reception, there will be issues with the SCL clock
stream and RCEN bit.
In I
receiving correct data.
If interrupts are enabled, disabling and
re-enabling the module requires a 2 T
2
C slave reception, the module may have problems
Issue Summary
CY
delay.
2010 Microchip Technology Inc.
Revisions
Affected
A1
X
X
X
X
X
X
X
(1)