AT90USB646-MUR Atmel, AT90USB646-MUR Datasheet - Page 283
AT90USB646-MUR
Manufacturer Part Number
AT90USB646-MUR
Description
MCU AVR 64K FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet
1.AT90USB646-MU.pdf
(461 pages)
Specifications of AT90USB646-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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7593K–AVR–11/09
• 7-6 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 5 - STALLRQ - STALL Request Handshake Bit
Set to request a STALL answer to the host for the next handshake.
Cleared by hardware when a new SETUP is received. Clearing by software has no effect.
See Section 22.11, page 271 for more details.
• 4 - STALLRQC - STALL Request Clear Handshake Bit
Set to disable the STALL handshake mechanism.
Cleared by hardware immediately after the set. Clearing by software has no effect.
See Section 22.11, page 271 for more details.
3
• RSTDT - Reset Data Toggle Bit
Set to automatically clear the data toggle sequence:
For OUT endpoint: the next received packet will have the data toggle 0.
For IN endpoint: the next packet to be sent will have the data toggle 0.
Cleared by hardware instantaneously. The firmware does not have to wait that the bit is cleared.
Clearing by software has no effect.
• 2 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 1 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 0 - EPEN - Endpoint Enable Bit
Set to enable the endpoint according to the device configuration. Endpoint 0 shall always be
enabled after a hardware or USB reset and participate in the device configuration.
Clear this bit to disable the endpoint. See Section 22.6, page 268 for more details.
• 7-6 - EPTYPE1:0 - Endpoint Type Bits
Set this bit according to the endpoint configuration:
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R/W
R
7
0
7
0
-
EPTYPE1:0
R/W
R
6
0
-
6
0
STALLRQ
W
5
0
R
5
0
-
STALLRQC
R
W
4
0
-
4
0
RSTDT
R
3
0
-
W
3
0
R
2
0
-
AT90USB64/128
2
R
0
-
R
1
0
-
R
1
0
-
EPDIR
R/W
EPEN
R/W
0
0
0
0
UECFG0X
UECONX
283
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