ATMEGA3290P-20AUR Atmel, ATMEGA3290P-20AUR Datasheet - Page 94
ATMEGA3290P-20AUR
Manufacturer Part Number
ATMEGA3290P-20AUR
Description
MCU AVR 32K FLASH 20MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA3290P-20AUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
Price
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14. 8-bit Timer/Counter0 with PWM
14.1
14.2
14.2.1
8021G–AVR–03/11
Features
Overview
Registers
•
•
•
•
•
•
•
Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simpli-
fied block diagram of the 8-bit Timer/Counter is shown in
of I/O pins, refer to
on page
device-specific I/O Register and bit locations are listed in the
155.
Figure 14-1. 8-bit Timer/Counter Block Diagram
The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Inter-
rupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt
Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Reg-
ister (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
Single Compare Unit Counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Frequency Generator
External Event Counter
10-bit Clock Prescaler
Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A)
3. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The
Timer/Counter
TCNTn
OCRn
”MLF/ Pinout ATmega329P” on page 2
=
direction
count
clear
BOTTOM
= 0
Control Logic
=
TCCRn
TOP
0xFF
clk
Tn
ATmega329P/3290P
Figure
Generation
Waveform
and
Clock Select
”Register Description” on page
”TQFP / Pinout ATmega3290P”
( From Prescaler )
Detector
14-1. For the actual placement
Edge
OCn
(Int.Req.)
TOVn
(Int.Req.)
OCn
Tn
T0
).
94
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