PIC24FJ192GB110-I/PT Microchip Technology, PIC24FJ192GB110-I/PT Datasheet - Page 8
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PIC24FJ192GB110-I/PT
Manufacturer Part Number
PIC24FJ192GB110-I/PT
Description
IC PIC MCU FLASH 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ128GA106-IPT.pdf
(52 pages)
2.PIC24FJ64GB106-IPT.pdf
(16 pages)
3.PIC24FJ64GB106-IPT.pdf
(352 pages)
4.PIC24FJ192GB108-IPT.pdf
(328 pages)
Specifications of PIC24FJ192GB110-I/PT
Program Memory Type
FLASH
Program Memory Size
192KB (65.5K x 24)
Package / Case
100-TFQFP
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
83
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
84
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUMA240014 - MODULE PLUG-IN PIC24
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ192GB110-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC24FJ256GB110 FAMILY
23. Module: SPI (Enhanced Buffer Modes)
24. Module: A/D Converter
25. Module: SPI (Enhanced Buffer Mode)
DS80369K-page 8
Note: This issue only applies to 64-pin devices
If the SPI event interrupt is configured to occur
when
(SISEL<2:0> = 111), the interrupt may actually
occur when the 7th byte is written to the buffer,
instead of the 8th byte. The other enhanced buffer
interrupts function as previously described.
Work around
Do not use the Full Buffer Interrupt mode. The
SPITBF bit (SPIxSTAT<1>) reliably indicates when
the enhanced FIFO buffer is full and can be polled
instead of using the Full Buffer Interrupt mode.
Affected Silicon Revisions
When using PGEC1 and PGED1 to debug an
application on any 64-pin devices in this family, all
voltage references will be disabled. This includes
V
conversion will always equal 0x3FF.
Work around
Use PGEC2 and PGED2 to debug any A/D
functionality.
Affected Silicon Revisions
In Enhanced Master mode, the SRMPT bit
(SPIxSTAT<7>) may erroneously become set for
several clock cycles in the middle of a FIFO transfer,
indicating that the shift register is empty when it is
not. This happens when both SPI clock prescalers
are set to values other than their maximum
(SPIxCON<4:2> ≠ 000 and SPIxCON<1:0> ≠ 00).
REF
A3
A3
X
X
+, V
in
PIC24FJ192GB106,
PIC24FJ64GB106).
A5
A5
the
this
REF
enhanced
-, AV
family
DD
(PIC24FJ256GB106,
and AV
FIFO
buffer
SS
. Any A/D
and
is
full
26. Module: Core (Code Protection)
27. Module: CTMU (A/D Trigger)
Work around
Set SISEL<2:0> (SPIxSTAT<4:2>) to ‘101’. This
configures the module to generate an SPI event
interrupt whenever the last bit is shifted out of the
shift register. When the SPIxIF flag becomes set,
the shift register is empty.
Affected Silicon Revisions
When general segment code protection has been
enabled (GCP Configuration bit is programmed),
applications are unable to write to the first
512 bytes of the program memory space (0000h
through 0200h). In applications that may require
the interrupt vectors to be changed during run
time, such as bootloaders, modifications to the
Interrupt Vector Tables (IVT) will not be possible.
Work around
Create two new Interrupt Vector Tables, one each
for the IVT and AIVT, in an area of program space
beyond the affected region. Map the addresses in
the old vector tables to the new tables. These new
tables can then be modified as needed to the
actual addresses of the ISRs.
Affected Silicon Revisions
The CTMU may not trigger an automatic A/D
conversion after the current source is turned off.
This happens even when the A/D trigger control
bit, CTTRIG (CTMUCON<8>), has been set.
Work around
Perform a manual A/D conversion by clearing
the SAMP bit (AD1CON1<1>) immediately after
the CTMU current source has been stopped.
Affected Silicon Revisions
A3
A3
A3
X
X
X
A5
A5
A5
2010 Microchip Technology Inc.