ATXMEGA32D4-MH Atmel, ATXMEGA32D4-MH Datasheet - Page 8
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ATXMEGA32D4-MH
Manufacturer Part Number
ATXMEGA32D4-MH
Description
IC MCU AVR 32KB FLASH 100VFBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Datasheet
1.ATXMEGA16D4-AU.pdf
(105 pages)
Specifications of ATXMEGA32D4-MH
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 12x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Processor Series
XMEGA
Core
AVR
Data Bus Width
8 bit, 16 bit
Data Ram Size
4 KB
Interface Type
SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
34
Number Of Timers
4
Operating Supply Voltage
2.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATXMEGA32D4-MH
Manufacturer:
Atmel
Quantity:
1 910
Company:
Part Number:
ATXMEGA32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
ATXMEGA32D4-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
6. AVR CPU
6.1
6.2
8135J–AVR–12/10
Features
Overview
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The XMEGA D4 uses the 8/16-bit AVR CPU. The main function of the CPU is program execu-
tion. The CPU must therefore be able to access memories, perform calculations and control
peripherals. Interrupt handling is described in a separate section.
the CPU block diagram.
Figure 6-1.
The AVR uses a Harvard architecture - with separate memories and buses for program and
data. Instructions in the program memory are executed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory.
8/16-bit high performance AVR RISC Architecture
32x8-bit registers directly connected to the ALU
Stack in RAM
Stack Pointer accessible in I/O memory space
Direct addressing of up to 16M Bytes of program and data memory
True 16/24-bit access to 16/24-bit I/O registers
Support for for both 8-, 16- and 32-bit Arithmetic
Configuration Change Protection of system critical features
– 138 instructions
– Hardware multiplier
Peripheral
Module 1
CPU block diagram
CONTROL
STATUS/
Program
Counter
OCD
Peripheral
Module 2
Instruction
Instruction
Program
Register
Memory
Decode
Flash
DATA BUS
SRAM
DATA BUS
ALU
EEPROM
32 x 8 General
Registers
Multiplier
Purpose
Figure 6-1 on page 8
PMIC
XMEGA D4
shows
8