PIC18LF252-I/SOG Microchip Technology, PIC18LF252-I/SOG Datasheet - Page 16
![IC MCU FLASH 16KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18LF252-I/SOG
Manufacturer Part Number
PIC18LF252-I/SOG
Description
IC MCU FLASH 16KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
Specifications of PIC18LF252-I/SOG
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18FXX2/XX8
3.3
Data EEPROM is accessed one byte at a time via an
Address Pointer, EEADR, and a data latch, EEDATA.
Data EEPROM is written by loading EEADR with the
desired memory location, EEDATA with the data to be
written, and initiating a memory write by appropriately
configuring the EECON1 and EECON2 registers. A
byte write automatically erases the location and writes
the new data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, the EEPGD bit must be cleared
(EECON1<7> = 0) and the CFGS bit must be cleared
(EECON1<6> = 0). The WREN bit must be set
(EECON1<2> = 1) to enable writes of any sort, and this
must be done prior to initiating a write sequence. The
write sequence is initiated by the setting the WR bit
(EECON1<1> = 1). It is strongly recommended that the
WREN bit be set only when absolutely necessary.
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h
and then, AAh, immediately prior to asserting the WR
bit in order for the write to occur.
The write will begin on the falling edge of the 4th SCLK
after the WR bit is set.
After the programming sequence terminates, SCLK
must still be held low for the time specified by
parameter P10 to allow high voltage discharge of the
memory array.
FIGURE 3-8:
DS39576C-page 16
SCLK
SDATA
Poll WR bit
Data EEPROM Programming
4-bit Command
1
0
2
0
3
0
SDATA
SCLK
4
0
DATA EEPROM WRITE TIMING
P5
BSF EECON1, WR
1
4-bit Command
1
0
2
2
0
15 16
3
0
4
0
P5A
P5
MOVF EECON1, W, 0
1
2
SDATA = Input
SDATA = Input
15 16
P5A
4-bit Command
1
0
Poll WR bit, Repeat Until Clear
FIGURE 3-7:
2
0
3
0
(see below)
4
0
P5
MOVWF TABLAT
1
No
2
Unlock Sequence
15 16
AAh - EECON2
55h - EECON2
PROGRAM DATA FLOW
Enable Write
Set Address
Start Write
Sequence
2010 Microchip Technology Inc.
Set Data
WR bit
Done?
clear?
Start
Done
P5A
Yes
Yes
(see Figure 4-6)
SDATA = Output
Shift Out Data
No
P10
16-bit Data
Payload
1
n
2
n