PIC18LF2420-I/SP Microchip Technology, PIC18LF2420-I/SP Datasheet - Page 4

• Manufacturer Part Number: PIC18LF2420-I/SP
• Description: IC MCU FLASH 8KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2420-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/USART
• On-chip Adc: 10-chx10-bit
• Number Of Timers: 4
• Core: PIC
• Processor Series: PIC18LF
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 768 B
• Data Rom Size: 256 B
• Mounting Style: Through Hole
• Height: 3.3 mm
• Length: 34.67 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2420/2520/4420/4520
7. Module: Resets (BOR)
1.
2.
3.
4.
5.
6.
DS80363C-page 4
An unexpected Reset may occur if the Brown-out
Reset module (BOR) is disabled, and then re-
enabled, when the High/Low-Voltage Detection
module (HLVD) is not enabled (HLVDCON<4> = 0).
This issue affects BOR modes: BOREN<1:0> = 10
and BOREN<1:0> = 01. In both of these modes, if
the BOR module is re-enabled while the device is
active, unexpected Resets may be generated.
Work around
If BOR is required, and power consumption is not
an
BOREN<1:0> = 10 mode, either switch to
BOREN<1:0> = 11 mode or enable the HLVD
(HLVDCON<4> = 1) prior to entering Sleep.
If power consumption is an issue and low power is
desired, Microchip does not recommend using
BOREN<1:0>
BOREN<1:0> = 01 and follow the steps below
when entering and exiting Sleep.
Disable
(RCON<6> = 0).
Enter Sleep mode (if desired).
After exiting Sleep mode, enable the HLVD
(HLVDCON<4> = 1).
Wait for the internal reference voltage (T
to stabilize (typically 20 s).
Re-enable
(RCON<6> = 1).
Disable the HLVD by clearing HLVDEN
(HLVDCON<4> = 0).
Date Codes that pertain to this issue:
All engineering and production devices.
issue,
BOR
use
BOR
=
BOREN<1:0>
by
10
by
mode.
clearing
setting
Instead,
=
SBOREN
SBOREN
11.
IRVST
use
For
)
8. Module: Enhanced Universal
1.
2.
3.
4.
5.
9. Module: Master Synchronous Serial Port
In rare situations when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
• The EUSART is re-enabled (RCSTA <7> = 1)
• A two-cycle instruction is executed
Work around
Add a 2-T
Disable
PIE1<5>, = 0).
Disable the EUSART (RCSTA <7>, = 0).
Re-enable the EUSART (RCSTA <7> = 1).
Re-enable Receive Interrupts (PIE1<5> = 1).
(This is the first T
Execute a NOP instruction.
(This is the second T
Date Codes that pertain to this issue:
All engineering and production devices.
When configured for I
MSSP module may not receive the correct data, in
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPBUF) is not
read after the SSPIF interrupt (PIR1<3>) has
occurred, but before the first rising clock edge of
the next byte being received.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
• Each time the SSPIF is set, read the SSPBUF
Date Codes that pertain to this issue:
All engineering and production devices.
RCSTA <7>, = 0)
clock stretching feature.
This
(SSPCON2<0>).
before the first rising clock edge of the next byte
being received.
is
CY
Synchronous Asynchronous
Receiver Transmitter (EUSART)
Receive
(MSSP)
delay after re-enabling the EUSART.
done
2
C slave reception, enable the
CY
 2009 Microchip Technology Inc.
delay.)
by
CY
Interrupts
2
delay.)
C™ slave reception, the
setting
the
(RCIE
SEN
bit,
bit