PIC24FJ192GB110-I/PF Microchip Technology, PIC24FJ192GB110-I/PF Datasheet - Page 220
![IC PIC MCU FLASH 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC24FJ192GB110-I/PF
Manufacturer Part Number
PIC24FJ192GB110-I/PF
Description
IC PIC MCU FLASH 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ128GA106-IPT.pdf
(52 pages)
2.PIC24FJ64GB106-IPT.pdf
(16 pages)
3.PIC24FJ64GB106-IPT.pdf
(352 pages)
4.PIC24FJ192GB108-IPT.pdf
(328 pages)
Specifications of PIC24FJ192GB110-I/PF
Core Size
16-Bit
Program Memory Size
192KB (65.5K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
83
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Controller Family/series
PIC24
No. Of I/o's
83
Ram Memory Size
16KB
Cpu Speed
32MHz
No. Of Timers
5
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
84
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ192GB110-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC24FJ128GA106-IPT PDF datasheet
- PIC24FJ64GB106-IPT PDF datasheet #2
- PIC24FJ64GB106-IPT PDF datasheet #3
- PIC24FJ192GB108-IPT PDF datasheet #4
- Current page: 220 of 328
- Download datasheet (6Mb)
PIC24FJ256GB110 FAMILY
REGISTER 17-17: U1IR: USB INTERRUPT STATUS REGISTER (HOST MODE ONLY)
DS39897B-page 218
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/K-0, HS
Note:
STALLIF
U-0
—
Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the
entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause
all set bits at the moment of the write to become cleared.
Unimplemented: Read as ‘0’
STALLIF: STALL Handshake Interrupt bit
1 = A STALL handshake was sent by the peripheral device during the handshake phase of the
0 = A STALL handshake has not been sent
ATTACHIF: Peripheral Attach Interrupt bit
1 = A peripheral attachment has been detected by the module; set if the bus state is not SE0 and there
0 = No peripheral attachement detected
RESUMEIF: Resume Interrupt bit
1 = A K-state is observed on the D+ or D- pin for 2.5 μs (differential ‘1’ for low speed, differential ‘0’ for
0 = No K-state observed
IDLEIF: Idle Detect Interrupt bit
1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
TRNIF: Token Processing Complete Interrupt bit
1 = Processing of current token is complete; read U1STAT register for endpoint information
0 = Processing of current token not complete; clear U1STAT register or load next token from U1STAT
SOFIF: Start-Of-Frame Token Interrupt bit
1 = A Start-Of-Frame token received by the peripheral or the Start-Of-Frame threshold reached by the
0 = No Start-Of-Frame token received or threshold reached
UERRIF: USB Error Condition Interrupt bit
1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set
0 = No unmasked error condition has occurred
DETACHIF: Detach Interrupt bit
1 = A peripheral detachment has been detected by the module; Reset state must be cleared before
0 = No peripheral detachment detected. Individual bits can only be cleared by writing a ‘1’ to the bit
ATTACHIF
R/K-0, HS
transaction in Device mode
has been no bus activity for 2.5 μs
full speed)
this bit
U-0
—
host
this bit can be reasserted
position as part of a word write operation on the entire register. Using Boolean instructions or bit-
wise operations to write to a single bit position will cause all set bits at the moment of the write to
become cleared.
K = Write ‘1’ to clear bit
‘1’ = Bit is set
RESUMEIF
R/K-0, HS
U-0
—
R/K-0, HS
IDLEIF
U-0
—
Preliminary
U = Unimplemented bit, read as ‘0’
HS = Hardware Settable bit
‘0’ = Bit is cleared
R/K-0, HS
TRNIF
U-0
—
R/K-0, HS
SOFIF
U-0
—
© 2008 Microchip Technology Inc.
x = Bit is unknown
UERRIF
U-0
R-0
—
DETACHIF
R/K-0, HS
U-0
—
bit 8
bit 0
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