PIC24HJ64GP204-I/PT Microchip Technology, PIC24HJ64GP204-I/PT Datasheet - Page 5
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PIC24HJ64GP204-I/PT
Manufacturer Part Number
PIC24HJ64GP204-I/PT
Description
IC PIC MCU FLASH 64K 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP302-ISO.pdf
(368 pages)
3.PIC24HJ32GP302-ISO.pdf
(8 pages)
4.PIC24HJ32GP302-ISO.pdf
(12 pages)
5.PIC24HJ32GP304-EML.pdf
(356 pages)
Specifications of PIC24HJ64GP204-I/PT
Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
35
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel / 12 bit, 13 Channel
Controller Family/series
PIC24
No. Of I/o's
35
Ram Memory Size
4KB
Cpu Speed
40MIPS
No. Of Timers
7
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ64GP204-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
5. Module: I
6. Module: I
7. Module: I
© 2010 Microchip Technology Inc.
The BCL bit in I2CSTAT can only be cleared with
Word instructions, and can be corrupted with byte
instructions and bit operations.
Work around
Use Word instructions to clear BCL.
Affected Silicon Revisions
If there are two I
them is acting as the Master receiver and the other
as the Slave transmitter. If both devices are
configured for 10-bit Addressing mode, and have
the same value in the A10 and A9 bits of their
addresses, then when the Slave select address is
sent from the Master, both the Master and Slave
acknowledge it. When the Master sends out the
read operation, both the Master and the Slave
enter into Read mode and both of them transmit
the data. The resultant data will be the ANDing of
the two transmissions.
Work around
In all I
A10 and A9 should be different.
Affected Silicon Revisions
When the I
slave with and address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather
acknowledges both address bytes.
Work around
None.
Affected Silicon Revisions
A1
A1
A1
X
X
X
2
C devices, the addresses as well as bits
A2
A2
A2
X
X
X
than
2
2
2
2
C
C
C
C module is configured as a 10-bit
A3
A3
A3
X
X
X
0x02;
2
C devices on the bus, one of
A4
A4
A4
X
X
X
however,
the
module
8. Module: I
9. Module: I
10. Module: I
With the I
external
associated with the SCL and SDA pins do not
reflect the actual digital logic levels on the pins.
Work around
If the SDA and/or SCL pins need to be polled,
these pins should be connected to other port pins
in order to be read correctly. This issue does not
affect the operation of the I
Affected Silicon Revisions
In 10-bit Addressing mode, some address
matches do not set the RBF flag or load the
receive register I2CxRCV, if the lower address
byte
particular, these include all addresses with the
form XX0000XXXX and XX1111XXXX, with the
following exceptions:
• 001111000X
• 011111001X
• 101111010X
• 111111011X
Work around
Ensure that the lower address byte in 10-bit
Addressing mode does not match any 7-bit
reserved addresses.
Affected Silicon Revisions
When the I
or Slave mode, after the ACKSTAT bit is set when
receiving a NACK, it may be cleared by the
reception of a Start or Stop bit.
Work around
Store the value of the ACKSTAT bit immediately
after receiving a NACK.
Affected Silicon Revisions
A1
A1
A1
X
X
X
matches
A2
A2
A2
X
X
X
2
interrupt
C module enabled, the PORT bits and
2
2
2
2
C module is operating in either Master
C
C
C
A3
A3
A3
X
X
X
the
A4
A4
A4
X
X
X
input
reserved
2
C module.
functions
DS80441F-page 5
addresses.
(if
any)
In