PIC16C662-04I/L Microchip Technology, PIC16C662-04I/L Datasheet - Page 70

• Manufacturer Part Number: PIC16C662-04I/L
• Description: IC MCU OTP 4KX14 COMP 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C662-04I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 176 B
• Interface Type: RS- 232
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Data Rom Size: 176 B
• Height: 3.87 mm
• Length: 16.59 mm
• Supply Voltage (max): 6 V
• Supply Voltage (min): 4 V
• Width: 16.59 mm
• For Use With: DVA16XL441 - ADAPTER DEVICE ICE 44PLCC309-1040 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1039 - ADAPTER 44-PLCC TO 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

PIC16C64X & PIC16C66X
9.8
Power-down mode is entered by executing a
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the
high, low, or hi-impedance).
For lowest current consumption in this mode, all I/O
pins should be either at V
circuitry drawing current from the I/O pin and the com-
parators and V
that are hi-impedance inputs should be pulled high or
low externally to avoid switching currents caused by
floating inputs. The T0CKI input should also be at V
or V
tion from on chip pull-ups on PORTB should be consid-
ered.
The MCLR pin must be at a logic high level (V
9.8.1
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
The first event will reset the device upon wake-up.
However the latter two events will wake the device and
then resume program execution. The TO and PD bits in
the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up is cleared when SLEEP is invoked. The TO
bit is cleared if WDT wake-up occurred.
FIGURE 9-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT
DS30559A-page 70
Note
INSTRUCTION FLOW
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction
fetched
Instruction
executed
CLKOUT(4)
SS
Any device reset
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from RB0/INT pin, RB Port change, or
the Comparator.
INT pin
1: XT, HS or LP oscillator mode assumed.
2: T
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
for lowest current consumption. The contribu-
OSC1
Power-Down Mode (SLEEP)
WAKE-UP FROM SLEEP
PC
OST
SLEEP
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4
REF
= 1024T
Inst(PC - 1)
PC
module should be disabled. I/O pins
instruction was executed (driving
OSC
(drawing not to scale) This delay will not be there for RC osc mode.
DD
Q1 Q2 Q3 Q4
, or V
Inst(PC + 1)
SLEEP
PC+1
SS
, with no external
Q1
Processor in
SLEEP
IHMC
SLEEP
PC+2
).
Preliminary
DD
T
OST
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 2)
Inst(PC + 1)
When the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the
set (enabled), the device executes the instruction after
the
rupt address (0004h). In cases where the execution of
the instruction following
user should have an
9.8.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag set, one of the following events will
occur:
• If the interrupt occurs before the execution of a
• If the interrupt occurs during or after the execution
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as an NOP.
To ensure that the WDT is clear, a CLRWDT instruction
should be executed before a SLEEP instruction.
PC+2
SLEEP instruction, the SLEEP instruction will com-
plete as an NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bit will not be cleared.
of a SLEEP instruction, the device will immediately
wake-up from sleep. The SLEEP instruction will be
completely executed before the wake-up. There-
fore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
SLEEP
WAKE-UP USING INTERRUPTS
Interrupt Latency
Dummy cycle
SLEEP
instruction and then branches to the inter-
(Note 2)
PC + 2
instruction is being executed, the
SLEEP
NOP
Q1 Q2 Q3 Q4
SLEEP
Inst(0004h)
Dummy cycle
1996 Microchip Technology Inc.
after the
0004h
instruction. If the GIE bit is
is not desirable, the
SLEEP
Q1 Q2 Q3 Q4
Inst(0005h)
Inst(0004h)
0005h
instruction.