ATMEGA168-15AZ Atmel, ATMEGA168-15AZ Datasheet - Page 209
![MCU AVR 16K FLASH 15MHZ 32-TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA168-15AZ
Manufacturer Part Number
ATMEGA168-15AZ
Description
MCU AVR 16K FLASH 15MHZ 32-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA168-15AZ.pdf
(340 pages)
Specifications of ATMEGA168-15AZ
Package / Case
32-TQFP, 32-VQFP
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
23
Eeprom Size
512 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
1K x 8
Program Memory Size
16KB (16K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
I²C, SPI, UART/USART
Core Size
8-Bit
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Interface Type
2-Wire/USART/Serial
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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19.5.2
19.5.3
19.5.4
7530I–AVR–02/10
Bit Rate Generator Unit
Bus Interface Unit
Address Match Unit
This unit controls the period of SCL when operating in a Master mode. The SCL period is con-
trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status
Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the
CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note
that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock
period. The SCL frequency is generated according to the following equation:
Note:
This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and
Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted,
or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also
contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Regis-
ter is not directly accessible by the application software. However, when receiving, it can be set
or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the
value of the received (N)ACK bit can be determined by the value in the TWSR.
The START/STOP Controller is responsible for generation and detection of START, REPEATED
START, and STOP conditions. The START/STOP controller is able to detect START and STOP
conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up
if addressed by a Master.
If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continu-
ously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost
an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate
status codes generated.
The Address Match unit checks if received address bytes match the seven-bit address in the
TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the
TWAR is written to one, all incoming address bits will also be compared against the General Call
address. Upon an address match, the Control Unit is informed, allowing correct action to be
taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR.
The Address Match unit is able to compare addresses even when the AVR MCU is in sleep
mode, enabling the MCU to wake up if addressed by a Master. If another interrupt (e.g., INT0)
occurs during TWI Power-down address match and wakes up the CPU, the TWI aborts opera-
tion and return to it’s idle state. If this cause any problems, ensure that TWI Address Match is the
only enabled interrupt when entering Power-down.
• TWBR = Value of the TWI Bit Rate Register.
• PrescalerValue = Value of the prescaler, see
TWBR should be 10 or higher if the TWI operates in Master mode. If TWBR is lower than 10, the
Master may produce an incorrect output on SDA and SCL for the reminder of the byte. The prob-
lem occurs when operating the TWI in Master mode, sending Start + SLA + R/W to a Slave (a
Slave does not need to be connected to the bus for the condition to happen).
SCL frequency
=
ATmega48/88/168 Automotive
------------------------------------------------------------------------------------------- -
16
+
2(TWBR)
CPU Clock frequency
Table 19-2 on page
PrescalerValue
212.
209
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