PIC18F4320T-I/PT Microchip Technology, PIC18F4320T-I/PT Datasheet - Page 35
PIC18F4320T-I/PT
Manufacturer Part Number
PIC18F4320T-I/PT
Description
IC MCU FLASH 4KX16 EEPROM 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18F1320-ISS.pdf
(36 pages)
4.PIC18F2220-ISO.pdf
(394 pages)
5.PIC18F2220-ISO.pdf
(6 pages)
6.PIC18F2220-ISO.pdf
(6 pages)
7.PIC18F2220-ISO.pdf
(8 pages)
8.PIC18F2220-ISO.pdf
(6 pages)
9.PIC18F2220-ISO.pdf
(6 pages)
Specifications of PIC18F4320T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4320T-I/PT
Manufacturer:
SAMSUNG
Quantity:
2 300
Company:
Part Number:
PIC18F4320T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18F1320-ISS PDF datasheet #3
- PIC18F2220-ISO PDF datasheet #4
- PIC18F2220-ISO PDF datasheet #5
- PIC18F2220-ISO PDF datasheet #6
- PIC18F2220-ISO PDF datasheet #7
- PIC18F2220-ISO PDF datasheet #8
- PIC18F2220-ISO PDF datasheet #9
- Current page: 35 of 394
- Download datasheet (7Mb)
3.3.1
This mode is unique among the three low-power Idle
modes in that it does not disable the primary system
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation, with its
more accurate primary clock source, since the clock
source does not have to “warm up” or transition from
another oscillator.
PRI_IDLE mode is entered by setting the IDLEN bit,
clearing the SCS bits and executing a SLEEP instruc-
tion. Although the CPU is disabled, the peripherals
continue to be clocked from the primary clock source
specified in Configuration Register 1H. The OSTS bit
remains set in PRI_IDLE mode (see Figure 3-3).
FIGURE 3-3:
FIGURE 3-4:
© 2007 Microchip Technology Inc.
CPU Clock
Peripheral
CPU Clock
Program
Peripheral
Counter
Program
Counter
OSC1
Clock
OSC1
Clock
PRI_IDLE MODE
Q1
TRANSITION TIMING TO PRI_IDLE MODE
TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE
Wake-up Event
Q2
PC
PC
CPU Start-up Delay
Q3
Q4
PIC18F2220/2320/4220/4320
Q1
PC + 2
When a wake-up event occurs, the CPU is clocked
from the primary clock source. A delay of approxi-
mately 10 μs is required between the wake-up event
and when code execution starts. This is required to
allow the CPU to become ready to execute instructions.
After the wake-up, the OSTS bit remains set. The
IDLEN and SCS bits are not affected by the wake-up
(see Figure 3-4).
Q1
Q2
PC + 2
Q3
DS39599G-page 33
Q4
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