AT32UC3B1256-Z1UR Atmel, AT32UC3B1256-Z1UR Datasheet - Page 505
AT32UC3B1256-Z1UR
Manufacturer Part Number
AT32UC3B1256-Z1UR
Description
MCU AVR32 256K FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B1256-Z1UR
Package / Case
48-QFN Exposed Pad
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
28
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 6x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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• ETRGEDG: External Trigger Edge Selection
• LDBDIS: Counter Clock Disable with RB Loading
• LDBSTOP: Counter Clock Stopped with RB Loading
• BURST: Burst Signal Selection
• CLKI: Clock Invert
• TCCLKS: Clock Selection
32059J–12/2010
ETRGEDG
TCCLKS
BURST
0
1
2
3
0
1
2
3
4
5
6
7
0
1
2
3
0: TIOB is used as an external trigger.
1: Counter clock is disabled when RB loading occurs.
0: Counter clock is not disabled when RB loading occurs.
1: Counter clock is stopped when RB loading occurs.
0: Counter clock is not stopped when RB loading occurs.
1: The counter is incremented on falling edge of the clock.
0: The counter is incremented on rising edge of the clock.
Burst Signal Selection
The clock is not gated by an external signal
XC0 is ANDed with the selected clock
XC1 is ANDed with the selected clock
XC2 is ANDed with the selected clock
Clock Selected
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
Edge
none
rising edge
falling edge
each edge
AT32UC3B
505
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