AT89C5131A-S3SUL Atmel, AT89C5131A-S3SUL Datasheet - Page 10

• Manufacturer Part Number: AT89C5131A-S3SUL
• Description: MCU 8051 32K FLASH USB 52-PLCC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-S3SUL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: 2-Wire, EUART, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

10
AT89C5131A-L
Table 11. System Signal Description
Table 12. Power Signal Description
Signal
AD[7:0]
Signal
Name
A[15:8]
Name
PSEN
AVDD
AVSS
VDD
RST
ALE
VSS
WR
RD
EA
Type
Type
PWR
PWR
GND
GND
I/O
I/O
I/O
I/O
I/O
O
O
I
Description
Multiplexed Address/Data LSB for external access
Data LSB for Slave port access (used for 8-bit and 16-bit modes)
Address Bus MSB for external access
Data MSB for Slave port access (used for 16-bit mode only)
Read Signal
Read signal asserted during external data memory read operation.
Control input for slave port read access cycles.
Write Signal
Write signal asserted during external data memory write operation.
Control input for slave write access cycles.
Reset
Holding this pin low for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage lower than V
This pin has an internal pull-up resistor which allows the device to be reset
by connecting a capacitor between this pin and VSS.
Asserting RST when the chip is in Idle mode or Power-down mode returns
the chip to normal operation.
This pin is set to 0 for at least 12 oscillator periods when an internal reset
occurs (hardware watchdog or Power monitor).
Address Latch Enable Output
The falling edge of ALE strobes the address into external latch. This signal
is active only when reading or writing external memory using MOVX
instructions.
Program
Test mode entry signal. This pin must be set to V
External Access Enable
This pin must be held low to force the device to fetch code from external
program memory starting at address 0000h. It is latched during reset and
cannot be dynamically changed during operation.
Description
Alternate Ground
AVSS is used to supply the on-chip PLL and the USB PAD.
Alternate Supply Voltage
AVDD is used to supply the on-chip PLL and the USB PAD.
Digital Ground
VSS is used to supply the buffer ring and the digital core.
Digital Supply Voltage
VDD is used to supply the buffer ring on all versions of the device.
It is also used to power the on-chip voltage regulator of the Standard
versions or the digital core of the Low Power versions.
IL
is applied, whether or not the oscillator is running.
DD
for normal operation.
4338A–USB–08/04
Alternate
Alternate
Function
Function
P0[7:0]
P2[7:0]
P3.7
P3.6
-
-
-
-
-
-
-
-