PIC24HJ64GP510-E/PF Microchip Technology, PIC24HJ64GP510-E/PF Datasheet - Page 5
![IC PIC MCU FLASH 32KX16 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC24HJ64GP510-E/PF
Manufacturer Part Number
PIC24HJ64GP510-E/PF
Description
IC PIC MCU FLASH 32KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ64GP206-IPT.pdf
(292 pages)
3.PIC24HJ64GP206-IPT.pdf
(8 pages)
4.PIC24HJ64GP206-IPT.pdf
(20 pages)
5.PIC24HJ64GP206-IPT.pdf
(26 pages)
Specifications of PIC24HJ64GP510-E/PF
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TQFP, 100-VQFP
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Module
ECAN
UART
ADC
SPI
SPI
I
I/O
2
C
Only those issues indicated in the last column apply to the current silicon revision.
Consumption
Sleep Mode
Generation
Operation
Character
SDO1 Pin
FRMDLY
Transmit
Feature
in Sleep
SILICON ISSUE SUMMARY (CONTINUED)
Current
Break
Slave
Mode
—
Number
Item
54.
55.
56.
57.
58.
59.
60.
The WAKIF bit in the CxINTF register cannot be cleared by
software instruction after the device has been interrupted from
Sleep by activity on the CAN bus.
After the ACKSTAT bit is set when receiving a NACK, it may
be cleared by the reception of a Start or Stop bit.
Writing to the SPIxBUF register as soon as TBF bit is cleared
will cause the SPI module to ignore written data.
The UART module will not generate back-to-back Break
characters.
The SDO1 pin may toggle while the device is being
programmed via PGECx/PGEDx pin pairs.
The SPI communication in Framed mode does not function
correctly if the Slave SPI frame delay bit (FRMDLY) is set to
‘1’.
If the ADC module is in an enabled state when the device
enters Sleep Mode, the power-down current (I
device may exceed the device data sheet specifications.
PIC24HJXXXGPX06/X08/X10
Issue Summary
PD
) of the
DS80444D-page 5
Revisions
A2 A3 A4
X
X
X
X
X
X
X
Affected
X
X
X
X
X
X
X
(1)
X
X
X
X
X
X
X