PIC16F767-I/SS Microchip Technology, PIC16F767-I/SS Datasheet - Page 229
PIC16F767-I/SS
Manufacturer Part Number
PIC16F767-I/SS
Description
IC PIC MCU FLASH 8KX14 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F737-ISP.pdf
(276 pages)
4.PIC16F737-ISP.pdf
(10 pages)
Specifications of PIC16F767-I/SS
Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC16F
No. Of I/o's
25
Ram Memory Size
368Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DBF777 - BOARD DAUGHTER ICEPIC3AC164307 - MODULE SKT FOR PM3 28SSOPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F767-I/SS
Manufacturer:
MICROCHI
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F737-ISP PDF datasheet #3
- PIC16F737-ISP PDF datasheet #4
- Current page: 229 of 688
- Download datasheet (3Mb)
15.3.3
1997 Microchip Technology Inc.
SPI Master SSPM3:SSPM0 = 00xxb
Typical Connection
MSb
PROCESSOR 1
Serial Input Buffer
Figure 15-2
(Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both
shift registers on their programmed clock edge, and latched on the edge of the clock specified by
the SMP bit. Both processors should be programmed to same Clock Polarity (CKP), then both
controllers would send and receive data at the same time. Whether the data is meaningful (or
dummy data) depends on the application software. This leads to three scenarios for data trans-
mission:
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data
Figure 15-2:
Shift Register
(SSPBUF)
(SSPSR)
shows a typical connection between two microcontrollers. The master controller
LSb
SPI Master/Slave Connection
SDO
SCK
SDI
Serial Clock
SDO
SCK
SDI
Section 15. SSP
SPI Slave SSPM3:SSPM0 = 010xb
MSb
Serial Input Buffer
Shift Register
PROCESSOR 2
(SSPBUF)
(SSPSR)
DS31015A-page 15-9
LSb
15
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