AT89C51IC2-SLSUM Atmel, AT89C51IC2-SLSUM Datasheet
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AT89C51IC2-SLSUM
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AT89C51IC2-SLSUM Summary of contents
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... Power-Off Flag • Power Supply: – 2.7 to 3.6 (3V Version) – 2.7 to 5.5V (5V Version) • Temperature Ranges: Commercial (0 to +70°C) and Industrial (-40°C to +85°C) • Packages: PLC44, VQFP44 Power Supply cc 8-bit Flash Microcontroller with 2-wire Interface AT89C51IC2 Rev. 4301D–8051–02/08 1 ...
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... V pin. CC The AT89C51IC2 retains all features of the 80C52 with 256 bytes of internal RAM, a 10-source 4-level interrupt controller and three timer/counters. In addition, the AT89C51IC2 has a 32 kHz Subsidiary clock Oscillator, a Programmable Counter Array, an XRAM of 1024 byte, a Hardware Watchdog Timer, a Keyboard Inter- ...
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Block Diagram Figure 1. Block Diagram XTAL1 XTAL2 ALE/PROG PSEN EA ( (2) 4301D–8051–02/08 (2) (2) Flash RAM EUART 256 + 32K BRG C51 CORE IB-bus CPU Parallel I/O Ports & Ext Bus Timer 0 ...
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... SFR Mapping AT89C51IC2 4 The Special Function Registers (SFRs) of the AT89C51IC2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, PI2 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • ...
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Table 2. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer DPL 82h Data Pointer Low byte DPH 83h Data Pointer High byte Table 3. System Management ...
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... TL2 CCh Timer/Counter 2 Low Byte Table 7. PCA SFRs Mnemo -nic Add Name CCON D8h PCA Timer/Counter Control CMOD D9h PCA Timer/Counter Mode CL E9h PCA Timer/Counter Low byte CH F9h PCA Timer/Counter High byte AT89C51IC2 TF1 TR1 TF0 GATE1 C/T1# M11 - - - TF2 EXF2 ...
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Table 7. PCA SFRs (Continued) Mnemo -nic Add Name CCAPM0 DAh PCA Timer/Counter Mode 0 CCAPM1 DBh PCA Timer/Counter Mode 1 CCAPM2 DCh PCA Timer/Counter Mode 2 CCAPM3 DDh PCA Timer/Counter Mode 3 CCAPM4 DEh PCA Timer/Counter Mode 4 CCAP0H ...
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... Synchronous Serial Data SSADR 96h Synchronous Serial Address Table 11. Keyboard Interface SFRs Mnemonic Add Name KBLS 9Ch Keyboard Level Selector KBE 9Dh Keyboard Input Enable KBF 9Eh Keyboard Flag Register AT89C51IC2 SSCR2 SSPE SSSTA SSSTO SSC4 SSC3 SSC2 SSC1 SSD7 SSD6 SSD5 ...
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Table 12. SFR Mapping Bit addressable 0/8 1/9 CH F8h 0000 0000 B F0h 0000 0000 CL E8h 0000 0000 ACC E0h 0000 0000 CCON CMOD D8h 00X0 0000 00XX X000 FCON (1) PSW D0h 0000 0000 XXXX 0000 T2CON ...
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... Pin Configurations Figure 2. Pin Configurations P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEx4/MOSI PI2.1/SDA P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEX4/MOSI AT89C51IC2 RST 10 P3.0/RxD 11 12 PLCC44 P3.1/TxD 13 P3.2/INT0 14 P3.3/INT1 15 P3.4/T0 16 P3.5/ RST 4 P3.0/RxD 5 VQFP44 1.4 PI2.1/SDA 6 P3.1/TxD 7 8 P3.2/INT0 P3.3/INT1 9 P3.4/T0 10 P3.5/ P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 PI2.0/SCL 33 ALE/PROG 32 PSEN 31 P2.7/A15 30 P2 ...
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... As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for AT89C51IC2 Port 1 include: 40 I/O P1.0: Input/Output I/O T2 (P1 ...
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... PI2.0 - PI2.1 34 AT89C51IC2 12 Type Name and Function 3 I/O P1.7: Input/Output: I/O CEX4: Capture/Compare External I/O for PCA module 4 I/O MOSI: SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller. ...
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Table 13. Pin Description for 40/44 Pin Packages (Continued) Pin Number Mnemonic PLCC44 VQFP44 1.4 RST 10 ALE/PROG 33 PSEN 4301D–8051–02/08 Type Name and Function SDA is the bidirectional 2-wire data line Reset: A high on this ...
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... Oscillators Overview Registers AT89C51IC2 14 Two oscillators are available for CPU: • OSCA used for high frequency MHz @5V +/- 10% • OSCB used for low frequency: 32.768 kHz Several operating modes are available and programmable by software: • to switch OSCA to OSCB and vice-versa • ...
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Table 15. OSCCON Register OSCCON- Oscillator Control Register (86h Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved Sub Clock Timer0 Cleared ...
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... AT89C51IC2 16 Table 17. PCON Register PCON - Power Control Register (87h SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode Serial port Mode bit 0 6 SMOD0 Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register. ...
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Functional Block Diagram Figure 3. Functional Oscillator Block Diagram PwdOscA FOSCA XtalA1 OscA XtalA2 OscAEn OSCCON PwdOscB XtalB1 XtalB2 OSCCON Operating Modes Reset Functional Modes Normal Modes 4301D–8051–02/08 Reload Reset CKRL 1 8-bit :2 0 Prescaler-Divider X2 CKCON0 CKRL=0xFF? OscB ...
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... Idle Modes Power Down Modes AT89C51IC2 18 • always possible to switch dynamically by software from OscA to OscB, and vice versa by changing CKS bit. • IDLE modes are achieved by using any instruction that writes into PCON.0 bit (IDL) • IDLE modes A and B depend on previous software sequence, prior to writing into PCON.0 bit: • ...
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Design Considerations Oscillators Control Prescaler Divider 4301D–8051–02/08 Table 18. Overview (Continued) PCON.1 PCON.0 OscBEn OscAEn • PwdOscA and PwdOscB signals are generated in the Clock generator and used ...
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... Timer 0: Clock Inputs AT89C51IC2 20 – F and F , for CKRL<>0xFF CLK CPU CLK PERIPH In X2 Mode CPU CLKPERIPH In X1 Mode CPU CLKPERIPH Figure 4. Timer 0: Clock Inputs FCLK PERIPH :6 T0 pin 0 Sub Clock 1 TMOD SCLKT0 OSCCON Gate INT0 TR0 Note: The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock. ...
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... The ALE disabling • Some enhanced features are also located in the UART and the timer 2 The AT89C51IC2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages: • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. ...
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... Figure 6. Mode Switching Waveforms XTALA1 XTALA1:2 X2 bit CPU clock STD Mode AT89C51IC2 22 F OSCA X2 Mode The X2 bit in the CKCON0 register (see Table 19) allow to switch from 12 clock periods per instruction to 6 clock periods and vice versa. At reset, the speed is setting according to X2 bit of Hardware Security Byte (HSB). By default, Standard mode is actived. Setting the X2 bit activates the X2 feature (X2 mode) ...
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Table 19. CKCON0 Register CKCON0 - Clock Control Register (8Fh SPIX2 WDX2 PCAX2 Bit Bit Number Mnemonic Description 2-wire clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, ...
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... AT89C51IC2 24 Table 20. CKCON1 Register CKCON1 - Clock Control Register (AFh Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 - Reserved 1 - Reserved SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) 0 SPIX2 Clear to select 6 clock periods per peripheral clock cycle. ...
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Dual Data Pointer Register Figure 7. Use of Dual Pointer 7 0 DPS AUXR1(A2H) 4301D–8051–02/08 The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which ...
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... ASSEMBLY LANGUAGE AT89C51IC2 26 ; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ...
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... Table 22. Table 22. Expanded RAM XRAM size AT89C51IC2 1024 The AT89C51IC2 has internal data memory that is mapped into four separate segments. The four segments are: 1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable. 2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only. ...
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... AT89C51IC2 28 • Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address 0A0h, rather than P2 (whose address is 0A0h). • The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions ...
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Table 23. AUXR Register AUXR - Auxiliary Register (8Eh Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit Reserved 6 - ...
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... Auto-Reload Mode AT89C51IC2 30 The Timer 2 in the AT89C51IC2 is the standard C52 the Timer 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded controlled by T2CON (Table 24) and T2MOD (Table 25) registers. Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F (timer operation) or external pin T2 (counter operation) as the timer clock input ...
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Figure 9. Auto-Reload Mode Up/Down Counter (DCEN = 1) F CLK PERIPH Programmable Clock- Output 4301D–8051–02/ (DOWN COUNTING RELOAD VALUE) FFh (8-bit) TL2 (8-bit) RCAP2L (8-bit) (UP COUNTING RELOAD VALUE) In the clock-out mode, timer 2 operates as ...
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... AT89C51IC2 32 Figure 10. Clock-Out Mode C/ CLK PERIPH T2 T2EX TR2 T2CON TH2 TL2 (8-bit) (8-bit) RCAP2H RCAP2L (8-bit) (8-bit) Toggle Q D T2OE T2MOD EXF2 T2CON EXEN2 T2CON OVEFLOW TIMER 2 INTERRUPT 4301D–8051–02/08 ...
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Table 24. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on timer 2 ...
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... AT89C51IC2 34 Table 25. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved 5 - The value read from this bit is indeterminate. Do not set this bit. ...
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Programmable Counter Array PCA 4301D–8051–02/08 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as the ...
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... Figure 11. PCA Timer/Counter Fclk periph /6 Fclk periph / 2 T0 OVF P1.2 Idle AT89C51IC2 bit up counter CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 To PCA modules overflow It CL CMOD ECF 0xD9 CCON 0xD8 4301D–8051–02/08 ...
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Table 26. CMOD Register CMOD - PCA Counter Mode Register (D9h CIDL WDTE - Bit Bit Number Mnemonic Description Counter Idle Control 7 CIDL Cleared to program the PCA Counter to continue functioning during idle Mode. ...
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... AT89C51IC2 38 Table 27. CCON Register CCON - PCA Counter Control Register (D8h Bit Bit Number Mnemonic Description PCA Counter Overflow flag Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF CMOD is set. CF may be set by either hardware or software but can only be cleared by software. ...
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Figure 12. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 CMOD.0 4301D–8051–02/ CCF4 CCF3 CCF2 CCF1 CCF0 ECF ECCFn CCAPMn.0 PCA Modules: each one of the five compare/capture modules has six ...
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... AT89C51IC2 40 Table 28 shows the CCAPMn settings for the various PCA functions. Table 28. CCAPMn Registers (n = 0-4) CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh) CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh) CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh) CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh) ...
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Table 29. PCA Module Modes (CCAPMn Registers) ECOMn CAPPn CAPNn MATn ...
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... AT89C51IC2 42 Table 31. CCAPnL Registers (n = 0-4) CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh) CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh) CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh) CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh) CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh) ...
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PCA Capture Mode Figure 13. PCA Capture Mode CF CR Cex.n ECOMn 16-bit Software Timer/ Compare Mode 4301D–8051–02/08 To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP ...
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... Figure 14. PCA Compare Mode and PCA Watchdog Timer Write to CCAPnL Reset Write to CCAPnH Enable 1 0 High Speed Output Mode AT89C51IC2 44 CF CCF4 CR CCAPnH CCAPnL Match 16 bit comparator CH CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CIDL WDTE Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit. Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’ ...
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Figure 15. PCA High Speed Output Mode Write to Reset CCA PnL Write to CCAPnH 0 1 Enable Pulse Width Modulator Mode 4301D–8051–02/ CCF4 CCF3 CCF2 CCF1 CCF0 CCAPnH CCAPnL Match 16 bit comparator CH CL PCA counter/timer ...
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... PCA Watchdog Timer AT89C51IC2 46 Figure 16. PCA PWM Mode Overflow Enable ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge ...
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... Serial I/O Port Framing Error Detection 4301D–8051–02/08 The serial I/O port in the AT89C51IC2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3) ...
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... Automatic Address Recognition Given Address AT89C51IC2 48 Figure 19. UART Timings in Modes 2 and 3 RXD Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 The automatic address recognition feature is enabled when the multiprocessor commu- nication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame ...
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Broadcast Address Reset Addresses 4301D–8051–02/08 The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB don’t-care bit; for slaves B and C, bit ...
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... Baud Rate Selection for UART for mode 1 and 3 AT89C51IC2 50 Table 35. SADDR Register SADDR - Slave Address Register (A9h Reset Value = 0000 0000b Not bit addressable The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. ...
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Internal Baud Rate Generator (BRG) Figure 21. Internal Baud Rate Peripheral clock BRR 4301D–8051–02/08 When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the BRL reload value, the value of ...
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... AT89C51IC2 52 Table 37. SCON Register SCON - Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. FE Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit. ...
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Table 38. Example of computed value when X2=1, SMOD1=1, SPD=1 Baud Rates F = 16.384 MHz OSCA BRL 115200 247 57600 238 38400 229 28800 220 19200 203 9600 149 4800 43 Table 39. Example of computed value when ...
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... UART Registers AT89C51IC2 54 Table 40. SADEN Register SADEN - Slave Address Mask Register for UART (B9h Reset Value = 0000 0000b Table 41. SADDR Register SADDR - Slave Address Register for UART (A9h Reset Value = 0000 0000b Table 42. SBUF Register SBUF - Serial Buffer Register for UART (99h) ...
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Table 44. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on timer 2 ...
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... AT89C51IC2 56 Table 45. PCON Register PCON - Power Control Register (87h SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 for UART 7 SMOD1 Set to select double baud rate in mode Serial port Mode bit 0 for UART 6 SMOD0 Cleared to select SM0 bit in SCON register. ...
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Table 46. BDRCON Register BDRCON - Baud Rate Control Register (9Bh Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit Reserved ...
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... Individual Enable AT89C51IC2 58 The AT89C51IC2 has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Two Wire Interface (I2C) interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 22. ...
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Registers 4301D–8051–02/08 The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at address 0043H, the I2C interrupt vector at 0043H and Keyboard interrupt vector is located at address 003BH. All other vectors addresses are ...
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... AT89C51IC2 60 Table 48. IENO Register IEN0 - Interrupt Enable Register (A8h ET2 Bit Bit Number Mnemonic Description Enable All interrupt bit 7 EA Cleared to disable all interrupts. Set to enable all interrupts. PCA interrupt enable bit 6 EC Cleared to disable. Set to enable. Timer 2 overflow interrupt Enable bit ...
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Table 49. IPL0 Register IPL0 - Interrupt Priority Register (B8h PPCL PT2L Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt ...
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... AT89C51IC2 62 Table 50. IPH0 Register IPH0 - Interrupt Priority High Register (B7h PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt Priority high bit. PPCHPPCLPriority Level 0 0 Lowest 6 PPCH Highest Timer 2 overflow interrupt Priority High bit ...
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Table 51. IEN1 Register IEN1 - Interrupt Enable Register (B1h Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved SPI interrupt Enable ...
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... AT89C51IC2 64 Table 52. IPL1 Register IPL1 - Interrupt Priority Register (B2h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved 5 - The value read from this bit is indeterminate. Do not set this bit. ...
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Table 53. IPH1 Register IPH1 - Interrupt Priority High Register (B3h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...
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... Interrupt Sources and Vector Addresses AT89C51IC2 66 Table 54. Interrupt Sources and Vector Addresses Number Polling Priority Interrupt Source Timer Timer Timer Keyboard Interrupt Request Reset INT0 IE0 TF0 INT1 IE1 IF1 UART RI+TI TF2+EXF2 PCA CF + CCFn (n = 0-4) KBDIT TWI TWIIT SPI SPIIT ...
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... Reset Cold Reset 4301D–8051–02/08 Two power reduction modes are implemented in the AT89C51IC2: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynami- cally divided by 2 using the X2 mode detailed in Section “ ...
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... Warm Reset Watchdog Reset AT89C51IC2 68 Table 1. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor Oscillator Start-Up Time 820 2.7 µF Note: These values assume V starts from 0V to the nominal value. If the time between 2 DD on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully discharged, leading to a bad reset sequence ...
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... In this case, the higher priority interrupt service routine is exe- cuted. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that puts the AT89C51IC2 into Power-down mode. can be lowered to save further ...
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... Idle External Power Down Internal Power Down External AT89C51IC2 70 Power-down Phase Oscillator Restart Phase Exit from Power-down by reset redefines all the SFRs, exit from Power-down by exter- nal interrupt does no affect the SFRs. Exit from Power-down by either reset or external interrupt does not affect the internal RAM content ...
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Serial Port Interface (SPI) Features Signal Description Master Output Slave Input (MOSI) Master Input Slave Output (MISO) SPI Serial Clock (SCK) Slave Select (SS) 4301D–8051–02/08 The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and ...
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... Baud Rate AT89C51IC2 72 drive the network. The Master may select each Slave device by software through port pins (Figure 27). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see Error conditions) ...
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Functional Description Operating Modes 4301D–8051–02/08 Figure 27 shows a detailed structure of the SPI Module. Figure 27. SPI Module Block Diagram FCLK PERIPH /4 Clock /8 /16 Divider /32 /64 /128 Clock Select SPR2 SPEN SSDIS SPI Interrupt Request The ...
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... Master Mode Slave Mode Transmission Formats AT89C51IC2 74 Figure 28. Full-Duplex Master-Slave Interconnection MISO 8-bit Shift register MOSI SPI SCK Clock Generator SS VDD Master MCU The SPI operates in Master mode when the Master bit, MSTR is set. Only one Master SPI device can initiate transmissions. Software begins the trans- mission from a Master SPI Module by writing to the Serial Peripheral Data Register (SPDAT) ...
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Figure 29. Data Transmission Format (CPHA = 0) SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point Figure 30. Data Transmission Format (CPHA = 1) ...
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... Write Collision (WCOL) Overrun Condition SS Error Flag (SSERR) Interrupts AT89C51IC2 76 The following flags in the SPSTA signal SPI error conditions: Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may be a multi-master conflict for system control ...
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Registers Serial Peripheral Control Register (SPCON) 4301D–8051–02/08 Figure 32. SPI Interrupt Requests Generation SPIF SPI Transmitter CPU Interrupt Request MODF SPI Receiver/error CPU Interrupt Request SSDIS There are three registers in the Module that provide control, status and data storage ...
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... Serial Peripheral Status Register (SPSTA) AT89C51IC2 78 Bit Number Bit Mnemonic Description SPR2 SPR1 SPR0 1 1 Reset Value = 0001 0100b Not bit addressable The Serial Peripheral Status Register contains flags to signal the following conditions: • Data transfer complete • Write collision • ...
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Serial Peripheral DATa Register (SPDAT) 4301D–8051–02/08 Bit Bit Number Mnemonic Description Reserved 1 - The value read from this bit is indeterminate. Do not set this bit. Reserved 0 - The value read from this bit is indeterminate. Do not ...
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... Power Reduction Mode AT89C51IC2 80 The AT89C51IC2 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power down modes. ...
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Registers 4301D–8051–02/08 Table 61. KBF Register KBF-Keyboard Flag Register (9Eh KBF7 KBF6 KBF5 Bit Bit Number Mnemonic Description Keyboard line 7 flag Set by hardware when the Port line 7 detects a programmed level. It generates a ...
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... AT89C51IC2 82 Table 62. KBE Register KBE-Keyboard Input Enable Register (9Dh KBE7 KBE6 KBE5 Bit Bit Number Mnemonic Description Keyboard line 7 Enable bit 7 KBE7 Cleared to enable standard I/O pin. Set to enable KBF.7 bit in KBF register to generate an interrupt request. Keyboard line 6 Enable bit 6 KBE6 Cleared to enable standard I/O pin ...
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Table 63. KBLS Register KBLS-Keyboard Level Selector Register (9Ch KBLS7 KBLS6 KBLS5 Bit Bit Number Mnemonic Description Keyboard line 7 Level Selection bit 7 KBLS7 Cleared to enable a low level detection on Port line 7. ...
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... Interface (TWI) AT89C51IC2 84 This section describes the 2-wire interface. In the rest of the section SSLC means Two- wire. The 2-wire bus is a bi-directional 2-wire serial communication standard designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs connected to them ...
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Figure 36. Block Diagram Input Filter SDA PI2.1 Output Stage Input Filter SCL PI2.0 Output Stage 4301D–8051–02/08 Address Register SSADR Comparator SSDAT Shift Register Arbitration & Sink Logic Timing & Control logic Serial clock generator Timer 1 overflow Control Register ...
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... Description SDA SCL AT89C51IC2 86 The CPU interfaces to the 2-wire logic via the following four 8-bit special function regis- ters: the Synchronous Serial Control register (SSCON; Table 73), the Synchronous Serial Data register (SSDAT; Table 74), the Synchronous Serial Control and Status reg- ister (SSCS; Table 75) and the Synchronous Serial Address register (SSADR Table 78). ...
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Master Transmitter Mode Master Receiver Mode 4301D–8051–02/ Read bit (high level at SDA) W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data ...
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... Slave Receiver Mode Slave Transmitter Mode AT89C51IC2 88 When the slave address and the direction bit have been transmitted and an acknowl- edgement bit has been received, the serial interrupt flag is set again and a number of status code in SSCS are possible. There are 40h, 48h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1) ...
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Miscellaneous States Notes CR2 4301D–8051–02/08 slave address followed by the data direction bit which must be at logic 1 (R) for SSLC to operate in the slave transmitter mode. After its own ...
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... Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave address or data byte Arbitration lost and addressed as slave From master to slave From slave to master AT89C51IC2 Data 18h A P 20h Other master continues ...
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Status Status of the Two- Code wire Bus and Two- SSSTA wire Hardware To/From SSDAT A START condition has 08h Write SLA+W been transmitted Write SLA+W A repeated START 10h condition has been transmitted Write SLA+R Write data byte No ...
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... Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or acknowledge bit Arbitration lost and addressed as slave From master to slave From slave to master AT89C51IC2 92 MR Data Data 50h 40h A P 48h Other master ...
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Status Status of the Two- Code wire Bus and Two- SSSTA wire Hardware To/From SSDAT A START condition has 08h Write SLA+R been transmitted Write SLA+R A repeated START 10h condition has been transmitted Write SLA+W No SSDAT action Arbitration ...
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... Reception of the general call address and one or more data bytes. Last data byte received is not acknowledged. Arbitration lost as master and addressed as slave by general call From master to slave From slave to master AT89C51IC2 94 S SLA W A 60h A 68h General Call ...
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Status Code Status of the 2-wire bus and (SSCS) 2-wire hardware Own SLA+W has been 60h received; ACK has been returned Arbitration lost in SLA+R/W as master; own SLA+W has been 68h received; ACK has been returned General call address ...
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... Previously addressed with general call; data has been 98h received; NOT ACK has been returned A STOP condition or repeated START condition has been A0h received while still addressed as slave AT89C51IC2 96 Application Software Response To/from SSDAT To SSCON STA STO SI Read data byte ...
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Figure 41. Format and State in the Slave Transmitter Mode Reception of the S own slave address and one or more data bytes Arbitration lost as master and addressed as slave Last data byte transmitted. Switched to not addressed slave ...
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... Data byte in SSDAT has been C0h transmitted; NOT ACK has been received Last data byte in SSDAT has C8h been transmitted (AA=0); ACK has been received AT89C51IC2 98 Application Software Response To/from SSDAT To SSCON STA STO No SSDAT action SSDAT action or ...
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Registers 4301D–8051–02/08 Table 73. SSCON Register SSCON - Synchronous Serial Control register (93h CR2 SSIE STA Bit Bit Number Mnemonic Description Control Rate bit 2 7 CR2 See Table 67. Synchronous Serial Interface Enable bit 6 SSIE ...
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... AT89C51IC2 100 Bit Bit Number Mnemonic Description 1 SD1 Address bit 1 or Data bit 1. 0 SD0 Address bit 0 (R/W) or Data bit 0. Table 75. SSCS (094h) read - Synchronous Serial Control and Status Register SC4 SC3 SC2 Table 76. SSCS Register: Read Mode - Reset Value = F8h ...
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Table 77. SSADR (096h) - Synchronus Serial Address Register (read/write Table 78. SSADR Register - Reset value = FEh Bit Bit Number Mnemonic Description 7 A7 Slave Address bit Slave ...
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... Hardware Watchdog Timer Using the WDT AT89C51IC2 102 The WDT is intended as a recovery method in situations where the CPU may be sub- jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H ...
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... WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT89C51IC2 while in Idle mode, the user should always set up a timer that will periodi- cally exit Idle, service the WDT, and re-enter Idle mode. ...
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... Power-off Flag AT89C51IC2 104 The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced still applied to the device and could be generated for example by an exit from CC power-down. The power-off flag (POF) is located in PCON register (Table 81). POF is set by hard- ware when V rises from 0 to its nominal voltage ...
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... Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the AT89C51IC2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 82 shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. ...
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... Reduced EMI Mode AT89C51IC2 106 The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches ...
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... EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51 but it is not identical and the commercially available programmers need to have support for the AT89C51IC2. The bootloader and the Application Programming Interface (API) routines are located in the BOOT ROM. ...
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... Software registers are in a special page of the Flash memory which can be accessed through the API or with the parallel programming modes. This page, called "Extra Flash Memory", is not in the internal Flash program memory addressing space. The only hardware register of the AT89C51IC2 is called Hardware Security Byte (HSB). Table 84. Hardware Security Byte (HSB ...
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... Several registers are used, in factory and by parallel programmers, to make copies of hardware registers contents. These values are used by Atmel ISP. These registers are in the "Extra Flash Memory" part of the Flash memory. This block is also called "XAF" or eXtra Array Flash. They are accessed in the following ways: • ...
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... The two lock bits provide different levels of protection for the on-chip code and data, when programmed as shown in Table 88. Default value Description FCh 101x 1011b 0FFh FFh 58h ATMEL D7h C51 X2, Electrically Erasable F7h AT89C51IC2 32KB AT89C51IC2 32KB, Revision EFh LB1 0 LB0 4301D–8051–02/08 ...
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... ISP After ISP After ISP In the AT89C51IC2, the lowest 32K of the 64 KB program memory address space is filled by internal Flash. When the EA pin is high, the processor fetches instructions from internal program Flash. Bus expansion for accessing program memory from 32K upward automatic since exter- nal instruction fetches occur automatically when the program counter exceeds 7FFFh (32K) ...
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... Bootloader Architecture Introduction Acronyms AT89C51IC2 112 The bootloader manages a communication according to a specific defined protocol to provide the whole access and service on Flash memory. Furthermore, all accesses and routines can be called from the user application. Figure 43. Diagram Context Description Access via Specific ...
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Functional Description Figure 44. Bootloader Functional Description Exernal Host with Specific Protocol Communication 4301D–8051–02/08 ISP Communication Management Flash Memory Management Flash Memory On the above diagram, the on-chip bootloader processes are: • ISP Communication Management The purpose of this process ...
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... Bootloader Functionality Introduction Figure 45. Hardware conditions typical sequence during power-on. AT89C51IC2 114 The bootloader can be activated by two means: Hardware conditions or regular boot process. The Hardware conditions ( PSEN = 0) during the Reset# falling edge force the on-chip bootloader execution. This allows an application to be built that will normally execute the end user’ ...
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... ENBOOT bit (AUXR1) is cleared Yes (PSEN = and ALE = 1 or not connected) FCON = 00h Hardware Condition? FCON = F0h BLJB = 1 BLJB!= 0 ENBOOT = 0 ? BLJB = 0 ENBOOT = 1 F800h yes = hardware boot FCON = 00h ? BSB = 00h ? SBV = FCh ? USER BOOT LOADER PC= [SBV]00h conditions Atmel BOOT LOADER 115 ...
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... ISP Protocol Description Physical Layer Frame Description AT89C51IC2 116 The UART used to transmit information has the following configuration: • Character: 8-bit data • Parity: none • Stop: 1 bit • Flow control: none • Baud rate: autobaud is performed by the bootloader to compute the baud rate choosen by the host ...
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Functional Description Software Security Bits (SSB) 4301D–8051–02/08 The SSB protects any Flash access from ISP command. The command "Program Software Security bit" can only write a higher priority level. There are three levels of security: • level 0: NO_SECURITY (FFh) ...
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... Full Chip Erase Checksum Error Flow Description Overview Communication Initialization AT89C51IC2 118 The ISP command "Full Chip Erase" erases all User Flash memory (fills with FFh) and sets some Bytes used by the bootloader at their default values: • BSB = FFh • SBV = FCh • ...
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... This information is then used to pro- gram the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the AT89C51IC2 to establish the baud rate. Table 91 shows the autobaud capability. ...
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... Send Write Command OR Wait Checksum Error COMMAND ABORTED OR Wait Security Error COMMAND ABORTED Wait COMMAND_OK COMMAND FINISHED AT89C51IC2 120 ":" ":" This flow is common to the following frames: • Flash/EEPROM Programming Data Frame • EOF or Atmel Frame (only Programming Atmel Frame) • ...
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... Example 4301D–8051–02/08 Programming Data (write 55h at address 0010h in the Flash 0010 HOST : 01 0010 BOOTLOADER Programming Atmel function (write SSB to level 0000 HOST : 02 0000 F5 BOOTLOADER Writing Frame (write BSB to 55h 0000 HOST : 03 0000 BOOTLOADER 121 ...
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... Wait Checksum Error COMMAND ABORTED Wait COMMAND_OK OR COMMAND FINISHED Wait Address not erased COMMAND FINISHED Example AT89C51IC2 122 Blank Check Command ’X’ & CR & LF ’.’ & CR & LF address & CR & LF Blank Check 0000 04 0000 7FFF 01 78 HOST : 05 0000 04 0000 7FFF ...
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Display Data Description Figure 51. Display Flow Host Send Display Command OR Wait Checksum Error COMMAND ABORTED OR Wait Security Error COMMAND ABORTED Wait Display Data All data read COMMAND FINISHED Note: The maximum size of block is 400h. To ...
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... Send Read Command OR Wait Checksum Error COMMAND ABORTED OR Wait Security Error COMMAND ABORTED Wait Value of Data COMMAND FINISHED Example AT89C51IC2 124 Display data from address 0000h to 0020h HOST : 05 0000 04 0000 0020 0000 04 0000 0020 00 D7 BOOTLOADER BOOTLOADER 0000=-----data------ CR LF BOOTLOADER ...
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ISP Commands Summary 4301D–8051–02/08 Table 92. ISP Commands Summary Command Command Name Data[0] 00h Program Data 03h Write Function Data[0:1] = start address Data [2:3] = end address 04h Display Function Data[4] = 00h -> Display data Data[4] = 01h ...
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... XXh READ SBV 07h XXh AT89C51IC2 126 Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made through a common interface, PGM_MTP. The programming functions are selected by setting up the microcontroller’ ...
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Table 93. API Call Summary (Continued) Command R1 A Number of PROGRAM DATA 09h byte to PAGE program Fuse value PROGRAM X2 FUSE 0Ah 00h or 01h Fuse value PROGRAM BLJB 0Ah FUSE 00h or 01h READ HSB 0Bh XXh ...
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... Input Low Voltage IL V Input High Voltage except RST, XTAL1 IH (9) V Input High Voltage RST, XTAL1 IH1 V Output Low Voltage, ports Output Low Voltage, port 0, ALE, PSEN OL1 V Output High Voltage, ports AT89C51IC2 128 Note: + 0.5V CC Min Typ -0.5 0 0 ( ...
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T = -40°C to +85° 0V =2.7V to 5.5V and MHz (both internal and external code execution =4.5V to 5.5V and MHz (internal ...
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... Typical are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V. 6. Under steady state (non-transient) conditions, I Maximum I per port pin Maximum I per 8-bit port: OL Port Ports 1, 2 and Maximum total I for all output pins AT89C51IC2 130 = 2.7V to 3.6V MHz Min Typ -0.5 0 0 (6) (6) 0 ...
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If I exceeds the test condition than the listed test conditions. 7. For other values, please contact your sales office. 8. Icc Flash Write operation current while an on-chip flash page write is on going. 4301D–8051–02/08 may exceed ...
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... Explanation of the AC Symbols External Program Memory Characteristics AT89C51IC2 132 Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for ...
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Table 95. AC Parameters for a Fix Clock Symbol -M Min LHLL T 5 AVLL T 5 LLAX T LLIV T 5 LLPL T 50 PLPH T PLIV T 0 PXIX T PXIZ T AVIV ...
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... External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 External Data Memory Characteristics AT89C51IC2 134 LHLL LLIV T LLPL T PLPH T LLAX T PLIV T T AVLL TPLAZ PXIX A0-A7 INSTR IN T AVIV ADDRESS A8-A15 Table 97. Symbol Description Symbol Parameter T RD Pulse Width ...
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Table 98. AC Parameters for a Fix Clock -M Symbol Min T 125 RLRH T 125 WLWH T RLDV T 0 RHDX T RHDZ T LLDV T AVDV T 45 LLWL T 70 AVWL T 5 QVWX T 155 ...
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... External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 AT89C51IC2 136 Standard Symbol Type Clock X2 Clock T Min RLRH T Min WLWH T Max 2 RLDV T Min x x RHDX T Max RHDZ T Max LLDV T Max 4 AVDV T Min 1 LLWL T Max 1 LLWL T Min AVWL T Min ...
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External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing - Shift Register Mode 4301D–8051–02/08 T LLDV T LLWL T AVDV T LLAX A0-A7 T RLAZ T AVWL ADDRESS A8-A15 OR SFR ...
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... Shift Register Timing Waveforms 0 INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI External Clock Drive Waveforms AC Testing Input/Output Waveforms Float Waveforms Clock Waveforms AT89C51IC2 138 XLXL T XHQX XHDX T XHDV VALID VALID VALID VALID V -0.5V CC 0.7V CC 0.2V -0.1 0.45V ...
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Figure 57. Internal Clock Signals STATE4 INTERNAL CLOCK P1 P2 XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT P2 (EXT) READ CYCLE WRITE CYCLE PORT OPERATION MOV PORT SRC MOV DEST ...
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... Ordering Information Table 102. Possible Order Entries Flash Memory Part Number Size AT89C51IC2-SLSCM AT89C51IC2-SLSIM AT89C51IC2-RLTIM AT89C51IC2-RLTIL AT89C51IC2-SLSIL AT89C51IC2-SLSUM 32K bytes AT89C51IC2-RLTUM 32K bytes AT89C51IC2-RLTUL 32K bytes AT89C51IC2-SLSUL 32K bytes AT89C51IC2 140 Temperature Supply Voltage Range OBSOLETE Industrial & Green 5V Industrial & ...
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Package Drawing PLCC44 4301D–8051–02/08 141 ...
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... Package Drawing VQFP44 AT89C51IC2 142 4301D–8051–02/08 ...
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Datasheet Revision History Changes from Rev. A 01/04 - Rev. B 01/06 Changes from Rev. B 01/06 - Rev. C 06/06 Changes from Rev. C 06/06 - Rev. D 02/08 4301D–8051–02/08 1. Added green product ordering information. 1. Correction to ...
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... Table of Contents AT89C51IC2 i Features ................................................................................................. 1 Description ............................................................................................ 2 Block Diagram ....................................................................................... 3 SFR Mapping ......................................................................................... 4 Pin Configurations .............................................................................. 10 Oscillators ........................................................................................... 14 Overview............................................................................................................. 14 Registers............................................................................................................. 14 Functional Block Diagram................................................................................... 17 Operating Modes ................................................................................................ 17 Design Considerations........................................................................................ 19 Timer 0: Clock Inputs.......................................................................................... 20 Enhanced Features ............................................................................. 21 X2 Feature and OSCA Clock Generation ........................................................... 21 Dual Data Pointer Register ................................................................ 25 Expanded RAM (XRAM) ..................................................................... 27 Timer 2 ................................................................................................. 30 Auto-Reload Mode ...
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Interrupt Sources and Vector Addresses............................................................ 66 Power Management ............................................................................ 67 Reset .................................................................................................................. 67 Reset Recommendation to Prevent Flash Corruption ........................................ 69 Idle Mode ............................................................................................................ 69 Power-down Mode.............................................................................................. 69 Serial Port Interface (SPI) ................................................................... 71 Features.............................................................................................................. 71 Signal Description............................................................................................... 71 ...
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... AT89C51IC2 iii DC Parameters for Low Voltage ....................................................................... 130 AC Parameters ................................................................................................. 132 Ordering Information ........................................................................ 140 Package Drawing .............................................................................. 141 PLCC44 ............................................................................................................ 141 Package Drawing .............................................................................. 142 VQFP44 ............................................................................................................ 142 Datasheet Revision History ............................................................. 143 Changes from Rev. A 01/04 - Rev. B 01/06 ..................................................... 143 Changes from Rev. B 01/06 - Rev. C 06/06 ..................................................... 143 Changes from Rev. C 06/06 - Rev. D 02/08 ..................................................... 143 Table of Contents .................................................................................. i 4301D– ...
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... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...