PIC16C71-20I/SO Microchip Technology, PIC16C71-20I/SO Datasheet - Page 23

• Manufacturer Part Number: PIC16C71-20I/SO
• Description: IC MCU OTP 1KX14 A/D 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C71-20I/SO

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Type: OTP
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 4x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC16C
• No. Of I/o's: 13
• Ram Memory Size: 36Byte
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Digital Ic Case Style: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MIL309-1011 - ADAPTER 18-SOIC TO 18-DIP309-1010 - ADAPTER 18-SOIC TO 18-DIPAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

4.3
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any reset, the upper bits of the
PC will be cleared. Figure 4-14 shows the two situa-
tions for the loading of the PC. The upper example in
the figure shows how the PC is loaded on a write to
PCL (PCLATH<4:0>
figure shows how the PC is loaded during a CALL or
GOTO instruction (PCLATH<4:3>
FIGURE 4-14: LOADING OF PC IN
4.3.1
A computed GOTO is accomplished by adding an off-
set to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
PC
PC
1997 Microchip Technology Inc.
12
12 11 10
2
PCL and PCLATH
COMPUTED GOTO
5
PCH
PCLATH<4:3>
PCH
PCLATH
PCLATH<4:0>
8
PCLATH
8
DIFFERENT SITUATIONS
7
7
PCH). The lower example in the
PCL
PCL
11
8
PCH).
0
0
Instruction with
PCL as
Destination
ALU
GOTO, CALL
Opcode <10:0>
4.3.2
The PIC16CXX family has an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
4.4
The PIC16C71X devices ignore both paging bits
(PCLATH<4:3>, which are used to access program
memory when more than one page is available. The
use of PCLATH<4:3> as general purpose read/write
bits for the PIC16C71X is not recommended since this
may affect upward compatibility with future products.
Note 1: There are no status bits to indicate stack
Note 2: There are no instructions/mnemonics
STACK
Program Memory Paging
overflow or stack underflow conditions.
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN,
tions, or the vectoring to an interrupt
address.
RETLW, and RETFIE instruc-
PIC16C71X
DS30272A-page 23