PIC16LF84-04/SO Microchip Technology, PIC16LF84-04/SO Datasheet - Page 49
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PIC16LF84-04/SO
Manufacturer Part Number
PIC16LF84-04/SO
Description
IC MCU FLASH 1KX14 EE 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF84-04/SO
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC16LF
No. Of I/o's
13
Eeprom Memory Size
64Byte
Ram Memory Size
68Byte
Cpu Speed
4MHz
No. Of Timers
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
PIC16LC84A-04/SO
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF84-04/SO
Manufacturer:
ON
Quantity:
34 000
FIGURE 8-17: INT PIN INTERRUPT TIMING
8.9.1
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION_REG<6>) is set,
or falling, if INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing control bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software via the interrupt service
routine before re-enabling this interrupt. The INT
interrupt can wake the processor from SLEEP
(Section 8.12) only if the INTE bit was set prior to going
into SLEEP. The status of the GIE bit decides whether
the processor branches to the interrupt vector
following wake-up.
8.9.2
An overflow (FFh
(INTCON<2>). The interrupt can be enabled/disabled
by setting/clearing enable bit T0IE (INTCON<5>)
(Section 6.0).
1998 Microchip Technology Inc.
INSTRUCTION FLOW
Note 1: INTF flag is sampled here (every Q1).
GIE bit
(INTCON<7>)
INTF flag
(INTCON<1>)
CLKOUT
INT pin
OSC1
Instruction
executed
Instruction
fetched
PC
2: Interrupt latency = 3-4Tcy where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
INT INTERRUPT
TMR0 INTERRUPT
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
on
3
the
Q1
00h) in TMR0 will set flag bit T0IF
Inst (PC-1)
RB0/INT
Inst (PC)
1
Q2
PC
Q3
4
pin,
Q4
5
Q1
the
Inst (PC+1)
Inst (PC)
Q2
1
INTF
PC+1
Q3
bit
Q4
Interrupt Latency
Q1
Dummy Cycle
Q2
8.9.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<3>)
(Section 5.2).
PC+1
—
Note 1: For a change on the I/O pin to be
Q3
PORT RB INTERRUPT
Q4
2
recognized, the pulse width must be at
least T
Q1
Dummy Cycle
Inst (0004h)
Q2
CY
0004h
wide.
Q3
PIC16F8X
Q4
Q1
DS30430C-page 49
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4