DSPIC33FJ64GP710-E/PT Microchip Technology, DSPIC33FJ64GP710-E/PT Datasheet - Page 310
![IC DSPIC MCU/DSP 64K 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
DSPIC33FJ64GP710-E/PT
Manufacturer Part Number
DSPIC33FJ64GP710-E/PT
Description
IC DSPIC MCU/DSP 64K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ64GP206-IPT.pdf
(322 pages)
3.DSPIC33FJ64GP206-IPT.pdf
(28 pages)
Specifications of DSPIC33FJ64GP710-E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TFQFP
For Use With
AC164333 - MODULE SKT FOR PM3 100QFPDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC24HJ12GP201-ISO PDF datasheet
- DSPIC33FJ64GP206-IPT PDF datasheet #2
- DSPIC33FJ64GP206-IPT PDF datasheet #3
- Current page: 310 of 322
- Download datasheet (5Mb)
dsPIC33FJXXXGPX06/X08/X10
TABLE A-1:
DS70286C-page 308
Section 8.0 “Oscillator Configuration”
Section 15.0 “Serial Peripheral Interface
(SPI)”
Section 16.0 “Inter-Integrated Circuit™
(I
Section 17.0 “Universal Asynchronous
Receiver Transmitter (UART)”
Section 18.0 “Enhanced CAN (ECAN™)
Module”
Section 19.0 “Data Converter Interface
(DCI) Module”
Section 20.0 “10-Bit/12-Bit
Analog-to-Digital Converter (ADC)”
Section 21.0 “Special Features”
2
C™)”
Section Name
MAJOR SECTION UPDATES (CONTINUED)
Updated the third clock source item (External Clock) in
Section 8.1.1 “System Clock sources”.
Added the center frequency in the OSCTUN register for the FRC
Tuning bits (TUN<5:0>) value 011111 and updated the center
frequency for bits value 011110 (Register 8-4).
Removed redundant information, which is now available in the
related section in the dsPIC33F Family Reference Manual, while
retaining the SPI Module Block Diagram (Figure 15-1).
Removed sections 16.3 through 16.13, while retaining the I
Diagram (Figure 16-1) (redundant information, which is now
available in the related section in the dsPIC33F Family Reference
Manual).
Removed sections 17.1 through 17.7 (redundant information, which
is now available in the related section in the dsPIC33F Family
Reference Manual).
Removed sections 18.4 through 18.6 (redundant information, which
is now available in the related section in the dsPIC33F Family
Reference Manual).
Updated Baud Rate Prescaler (BRP<5:0>) bit values in the CiCFG1
register (Register 18-9).
Changed default bit value from ‘0’ to ‘1’ for bits 6 through 15
(FLTEN6-FLTEN15) in the CiFEN1 register (Register 18-11).
Removed sections 19.3 through 19.7 (redundant information, which
is now available in the related section in the dsPIC33F Family
Reference Manual).
Removed Equation 20-1 (ADC Conversion Clock Period) and Figure
20-3 (ADC Transfer Function (10-Bit Example).
Updated AN14 and AN15 ADC values in the ADC2 Module Block
Diagram (FIGURE 20-2: “ADC2 Module Block Diagram
Added Note 2 to ADC Conversion Clock Period Block Diagram
(Figure 20-3).
Updated ADC Conversion Clock Select bits in the ADxCON3
register from ADCS<5:0> to ADCS<7:0>. Any references to these
bits have also been updated throughout this data sheet
(Register 20-3).
Added Note to ADxCHS0 register (Register 21-6).
Updated address 0xF8000E in the Device Configuration Register
Map (Table 21-1).
Added FICD register content (BKBUG, COE, JTAGEN and
ICS<1:0>) to the dsPIC33F Configuration Bits Description and
removed the last two rows (Table 21-2).
Added a Note after the second paragraph in Section 21.2 “On-Chip
Voltage Regulator”.
Update Description
© 2009 Microchip Technology Inc.
(1)
2
”).
C Block
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