PIC18LF4520-I/PT Microchip Technology, PIC18LF4520-I/PT Datasheet - Page 265

• Manufacturer Part Number: PIC18LF4520-I/PT
• Description: IC MCU FLASH 16KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4520-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: MSSP/SPI/I2C/PSP/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

23.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
FIGURE 23-5:
TABLE 23-3:
© 2008 Microchip Technology Inc.
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded cells are unimplemented.
Note 1:
®
devices.
File Name
Program Verification and
Code Protection
Unimplemented in PIC18F2420/4420 devices; maintain this bit set.
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
(PIC18F2420/4420)
SUMMARY OF CODE PROTECTION REGISTERS
Unimplemented
Boot Block
16 Kbytes
Read ‘0’s
Block 0
Block 1
CODE-PROTECTED PROGRAM MEMORY FOR
PIC18F2420/2520/4420/4520
MEMORY SIZE/DEVICE
WRTD
Bit 7
CPD
—
—
—
—
EBTRB
(PIC18F2520/4520)
WRTB
Bit 6
CPB
Unimplemented
—
—
—
32 Kbytes
Boot Block
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
PIC18F2420/2520/4420/4520
WRTC
Bit 5
—
—
—
—
—
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
1FFFFFh
Address
Range
Bit 4
—
—
—
—
—
—
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 23-5 shows the program memory organization
for 16 and 32-Kbyte devices and the specific code pro-
tection bit associated with each block. The actual
locations of the bits are summarized in Table 23-3.
(Unimplemented Memory Space)
EBTR3
WRT3
CP3
Bit 3
—
—
—
Block Code Protection
CPB, WRTB, EBTRB
(1)
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
(1)
(1)
Controlled By:
EBTR2
WRT2
CP2
Bit 2
—
—
—
(1)
(1)
(1)
EBTR1
WRT1
Bit 1
CP1
DS39631E-page 263
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—