PIC18LF4520-I/PT Microchip Technology, PIC18LF4520-I/PT Datasheet - Page 4
![IC MCU FLASH 16KX16 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF4520-I/PT
Manufacturer Part Number
PIC18LF4520-I/PT
Description
IC MCU FLASH 16KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2420-IML.pdf
(412 pages)
4.PIC18F2420-IML.pdf
(16 pages)
5.PIC18F2420-IML.pdf
(8 pages)
6.PIC18F2420-IML.pdf
(6 pages)
7.PIC18F2420-IML.pdf
(8 pages)
8.PIC18F2420-IML.pdf
(4 pages)
9.PIC18F4420-IP.pdf
(390 pages)
Specifications of PIC18LF4520-I/PT
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
MSSP/SPI/I2C/PSP/USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
Package
44TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF4520-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18LF4520-I/PT
Manufacturer:
MICROCHI
Quantity:
20 000
PIC18F2420/2520/4420/4520
7. Module: Resets (BOR)
1.
2.
3.
4.
5.
6.
DS80363C-page 4
An unexpected Reset may occur if the Brown-out
Reset module (BOR) is disabled, and then re-
enabled, when the High/Low-Voltage Detection
module (HLVD) is not enabled (HLVDCON<4> = 0).
This issue affects BOR modes: BOREN<1:0> = 10
and BOREN<1:0> = 01. In both of these modes, if
the BOR module is re-enabled while the device is
active, unexpected Resets may be generated.
Work around
If BOR is required, and power consumption is not
an
BOREN<1:0> = 10 mode, either switch to
BOREN<1:0> = 11 mode or enable the HLVD
(HLVDCON<4> = 1) prior to entering Sleep.
If power consumption is an issue and low power is
desired, Microchip does not recommend using
BOREN<1:0>
BOREN<1:0> = 01 and follow the steps below
when entering and exiting Sleep.
Disable
(RCON<6> = 0).
Enter Sleep mode (if desired).
After exiting Sleep mode, enable the HLVD
(HLVDCON<4> = 1).
Wait for the internal reference voltage (T
to stabilize (typically 20 s).
Re-enable
(RCON<6> = 1).
Disable the HLVD by clearing HLVDEN
(HLVDCON<4> = 0).
Date Codes that pertain to this issue:
All engineering and production devices.
issue,
BOR
use
BOR
=
BOREN<1:0>
by
10
by
mode.
clearing
setting
Instead,
=
SBOREN
SBOREN
11.
IRVST
use
For
)
8. Module: Enhanced Universal
1.
2.
3.
4.
5.
9. Module: Master Synchronous Serial Port
In rare situations when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
• The EUSART is re-enabled (RCSTA <7> = 1)
• A two-cycle instruction is executed
Work around
Add a 2-T
Disable
PIE1<5>, = 0).
Disable the EUSART (RCSTA <7>, = 0).
Re-enable the EUSART (RCSTA <7> = 1).
Re-enable Receive Interrupts (PIE1<5> = 1).
(This is the first T
Execute a NOP instruction.
(This is the second T
Date Codes that pertain to this issue:
All engineering and production devices.
When configured for I
MSSP module may not receive the correct data, in
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPBUF) is not
read after the SSPIF interrupt (PIR1<3>) has
occurred, but before the first rising clock edge of
the next byte being received.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
• Each time the SSPIF is set, read the SSPBUF
Date Codes that pertain to this issue:
All engineering and production devices.
RCSTA <7>, = 0)
clock stretching feature.
This
(SSPCON2<0>).
before the first rising clock edge of the next byte
being received.
is
CY
Synchronous Asynchronous
Receiver Transmitter (EUSART)
Receive
(MSSP)
delay after re-enabling the EUSART.
done
2
C slave reception, enable the
CY
2009 Microchip Technology Inc.
delay.)
by
CY
Interrupts
2
delay.)
C™ slave reception, the
setting
the
(RCIE
SEN
bit,
bit