DSPIC33FJ128MC802-I/SO Microchip Technology, DSPIC33FJ128MC802-I/SO Datasheet - Page 327
![IC DSPIC MCU/DSP 128K 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
DSPIC33FJ128MC802-I/SO
Manufacturer Part Number
DSPIC33FJ128MC802-I/SO
Description
IC DSPIC MCU/DSP 128K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
2.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
3.DSPIC33FJ64MC202-ESO.pdf
(424 pages)
Specifications of DSPIC33FJ128MC802-I/SO
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC302-ISO PDF datasheet #2
- DSPIC33FJ64MC202-ESO PDF datasheet #3
- Current page: 327 of 436
- Download datasheet (6Mb)
28.5
dsPIC33FJ32MC302/304,
and dsPIC33FJ128MCX02/X04 devices implement a
JTAG interface, which supports boundary scan device
testing, as well as in-circuit programming. Detailed
information on this interface is provided in future
revisions of the document.
28.6
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 devices can be
serially programmed while in the end application circuit.
This is done with two lines for clock and data and three
other lines for power, ground and the programming
sequence. Serial programming allows customers to
manufacture boards with unprogrammed devices and
then program the digital signal controller just before
shipping the product. Serial programming also allows
the most recent firmware or a custom firmware to be
programmed. Refer to the “dsPIC33F/PIC24H Flash
Programming Specification” (DS70152) for details
about In-Circuit Serial Programming (ICSP).
Any of the three pairs of programming clock/data pins
can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
28.7
When MPLAB
circuit debugging functionality is enabled. This function
allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pin functions.
Any of the three pairs of debugging clock/data pins can
be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, V
pin pair. In addition, when the feature is enabled, some
of the resources are not available for general use.
These resources include the first 80 bytes of data RAM
and two I/O pins.
© 2011 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
Note:
JTAG Interface
In-Circuit Debugger
DD
In-Circuit Serial Programming
Refer to Section 24. “Programming and
Diagnostics”
dsPIC33F/PIC24H
Manual for further information on usage,
configuration and operation of the JTAG
interface.
, V
®
SS
ICD 2 is selected as a debugger, the in-
, PGC, PGD and the PGECx/PGEDx
dsPIC33FJ64MCX02/X04
(DS70207)
Family
Reference
of
the
28.8
The
dsPIC33FJ128MCX02/X04 devices offer advanced
implementation of CodeGuard Security that supports
BS, SS and GS while, the dsPIC33FJ32MC302/304
devices offer the intermediate level of CodeGuard
Security that supports only BS and GS. CodeGuard
Security enables multiple parties to securely share
resources (memory, interrupts and peripherals) on a
single chip. This feature helps protect individual
Intellectual Property in collaborative system designs.
When coupled with software encryption libraries,
CodeGuard Security can be used to securely update
Flash even when multiple IPs reside on the single chip.
The code protection features vary depending on the
actual dsPIC33F implemented. The following sections
provide an overview of these features.
Secure segment and RAM protection is implemented
on
dsPIC33FJ128MCX02/X04
dsPIC33FJ32MC302/304 devices do not support
secure segment and RAM protection.
Note:
the
Code Protection and CodeGuard
Security
Refer to Section 23. “CodeGuard™
Security” (DS70199) of the dsPIC33F/
PIC24H Family Reference Manual for
further
configuration
CodeGuard Security.
dsPIC33FJ64MCX02/X04
dsPIC33FJ64MCX02/X04
information
and
devices.
DS70291E-page 327
operation
on
usage,
and
and
The
of
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