DSPIC33FJ128MC802-I/SO Microchip Technology, DSPIC33FJ128MC802-I/SO Datasheet - Page 67
![IC DSPIC MCU/DSP 128K 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
DSPIC33FJ128MC802-I/SO
Manufacturer Part Number
DSPIC33FJ128MC802-I/SO
Description
IC DSPIC MCU/DSP 128K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
2.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
3.DSPIC33FJ64MC202-ESO.pdf
(424 pages)
Specifications of DSPIC33FJ128MC802-I/SO
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC302-ISO PDF datasheet #2
- DSPIC33FJ64MC202-ESO PDF datasheet #3
- Current page: 67 of 424
- Download datasheet (6Mb)
4.2.7
In addition to its use as a working register, the W15
register
dsPIC33FJ64MCX02/X04
dsPIC33FJ128MCX02/X04 devices is also used as a
software Stack Pointer. The Stack Pointer always
points to the first available free word and grows from
lower to higher addresses. It pre-decrements for stack
pops and post-increments for stack pushes, as shown
in Figure 4-6. For a PC push during any CALL instruc-
tion, the MSb of the PC is zero-extended before the
push, ensuring that the MSb is always clear.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM<0> is forced to ‘0’
because all stack operations must be word aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error
trap does not occur. The stack error trap occurs on a
subsequent push operation. For example, to cause a
stack error trap when the stack grows beyond address
0x2000 in RAM, initialize the SPLIM with the value
0x1FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-6:
© 2009 Microchip Technology Inc.
0x0000
Note:
15
000000000
SOFTWARE STACK
A PC push during exception processing
concatenates the SRL register to the MSb
of the PC prior to the push.
in
<Free Word>
PC<15:0>
the
PC<22:16>
CALL STACK FRAME
dsPIC33FJ32MC302/304,
0
POP : [--W15]
PUSH : [W15++]
W15 (before CALL)
W15 (after CALL)
and
Preliminary
4.2.8
The dsPIC33F product family supports Data RAM
protection features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessible only from the Boot
Segment Flash code when enabled. SSRAM (Secure
RAM segment for RAM) is accessible only from the
Secure Segment Flash code when enabled. See
Table 4-1 for an overview of the BSRAM and SSRAM
SFRs.
4.3
The addressing modes shown in Table 4-40 form the
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
4.3.1
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
4.3.2
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (that is,
the addressing mode can only be register direct), which
is referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or a data memory
location.
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
Note:
Instruction Addressing Modes
The
DATA RAM PROTECTION FEATURE
FILE REGISTER INSTRUCTIONS
MCU INSTRUCTIONS
Not all instructions support all the
addressing modes given above. Individual
instructions can support different subsets
of these addressing modes.
following
addressing
DS70291D-page 67
modes
are
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