DSPIC33FJ128GP710-E/PT Microchip Technology, DSPIC33FJ128GP710-E/PT Datasheet - Page 4
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DSPIC33FJ128GP710-E/PT
Manufacturer Part Number
DSPIC33FJ128GP710-E/PT
Description
IC DSPIC MCU/DSP 128K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ64GP206-IPT.pdf
(322 pages)
3.DSPIC33FJ64GP206-IPT.pdf
(28 pages)
Specifications of DSPIC33FJ128GP710-E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TFQFP
For Use With
AC164333 - MODULE SKT FOR PM3 100QFPDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
dsPIC33F
Timers/Capture/Compare/PWM
• Timer/Counters: up to nine 16-bit timers:
• Input Capture (up to 8 channels):
• Output Compare (up to 8 channels):
Communication Modules
• 3-wire SPI™ (up to 2 modules):
• I
• UART (up to 2 modules):
• Data Conversion Interface (DCI) module:
• Enhanced CAN 2.0B active (up to 2 modules):
DS70155C-page 2
- Can pair up to make four 32-bit timers
- 1 timer runs as Real-Time Clock with external
- Programmable prescaler
- Capture on up, down or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
- Single or Dual 16-Bit Compare mode
- 16-Bit Glitchless PWM mode
- Framing supports I/O interface to simple
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
- 8-word FIFO buffers
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Address masking
- Interrupt-on-address bit detect
- Wake-up-on-Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
- IrDA
- High-Speed Baud mode
- Codec interface
- Supports I
- Up to 16-bit data words, up to 16 words per
- 4-word deep TX and RX buffers
- Up to 8 transmit and up to 16 receive buffers
- 16 receive filters and 3 masks
- Loopback, Listen Only and Listen All
- Wake-up on CAN message
- FIFO mode using DMA
2
C™ (up to 2 modules):
32 kHz oscillator
codecs
sampling modes
frame
Messages modes for diagnostics and bus
monitoring
®
encoding and decoding in hardware
2
S and AC’97 protocols
Preliminary
Motor Control Peripherals
• Motor Control PWM (up to 8 channels):
• Quadrature Encoder Interface module:
Analog-to-Digital Converters
• Up to two 10-bit or 12-bit A/D modules in a device
• 10-bit 2.2 Msps or 12-bit 1 Msps conversion:
CMOS Flash Technology
• Low-power, high-speed Flash technology
• Fully static design
• 3.3V (+/- 10%) operating voltage
• Industrial temperature
• Low-power consumption
Packaging:
• 100-pin TQFP (14x14x1 mm and 12x12x1 mm)
• 80-pin TQFP (12x12x1 mm)
• 64-pin TQFP (10x10x1 mm)
- 4 duty cycle generators
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge or center-aligned
- Manual output override control
- Up to 2 Fault inputs
- Trigger for A/D conversions
- PWM frequency for 16-bit resolution
- PWM frequency for 11-bit resolution
- Phase A, Phase B and index pulse input
- 16-bit up/down position counter
- Count direction status
- Position Measurement (x2 and x4) mode
- Programmable digital noise filters on inputs
- Alternate 16-bit Timer/Counter mode
- Interrupt on position counter rollover/
- 2 or 4 simultaneous samples
- Up to 32 input channels with auto-scanning
- 16-deep result buffer
- Conversion start can be manual or
- Conversion possible in Sleep mode
- ±1 LSB max integral nonlinearity
- ±1 LSB max differential nonlinearity
Note:
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
underflow
synchronized with 1 of 4 trigger sources
See Table 1-1 and Table 1-2 for exact
peripheral features per device.
© 2005 Microchip Technology Inc.