PIC18F448-E/P Microchip Technology, PIC18F448-E/P Datasheet - Page 249
PIC18F448-E/P
Manufacturer Part Number
PIC18F448-E/P
Description
IC MCU FLASH 8KX16 W/CAN 40-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18LF242-ISO.pdf
(36 pages)
2.PIC18F248-ISO.pdf
(402 pages)
3.PIC18F248-ISO.pdf
(8 pages)
Specifications of PIC18F448-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F448-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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20.4
Figure 20-4 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conver-
sion. The A/D Result register pair will not be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the last value written to the ADRESH:ADRESL
registers). After the A/D conversion is aborted, a 2 T
wait is required before the next acquisition is started.
After this 2 T
channel is automatically started.
FIGURE 20-3:
© 2006 Microchip Technology Inc.
Note:
A/D Conversions
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
AD
7
0000 00
wait, acquisition on the selected
ADRESH
A/D RESULT JUSTIFICATION
Right Justified
2 1 0 7
ADFM = 1
10-bit Result
ADRESL
0
AD
10-bit Result
20.4.1
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16 bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 20-3 shows the operation of the A/D result justi-
fication. The extra bits are loaded with ‘0’s. When an
A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
7
ADRESH
10-bit Result
A/D RESULT REGISTERS
ADFM = 0
Left Justified
0 7 6 5
PIC18FXX8
ADRESL
0000 00
DS41159E-page 247
0
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