AT90CAN32-16MU Atmel, AT90CAN32-16MU Datasheet - Page 417
![IC MCU AVR 32K FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN32-16MU
Manufacturer Part Number
AT90CAN32-16MU
Description
IC MCU AVR 32K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN32-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Processor Series
AT90CANx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
2
Operating Supply Voltage
0.5 V to 0.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
90C
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
2KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
QFN EP
Package
64QFN EP
Family Name
90C
Maximum Speed
16 MHz
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90CAN32-16MU
Manufacturer:
ATMEL
Quantity:
717
- Current page: 417 of 428
- Download datasheet (6Mb)
7679H–CAN–08/08
Let’s consider 4 sections in the Flash, described below:
Table 33-1.
Failing cases :
7. CAN acknowledge error in 3-sample mode with prescaler =1
6. CAN transmission after 3-bit intermission
Bootsize=4096 Words
Bootsize=2048 Words
Bootsize=1024 Words
Bootsize=512 Words
LPM instruction
LPM instruction
LPM instruction
LPM instruction
Problem fix / workaround
If protection level 3 is mandatory, the LPM instruction must be moved outside the failing
sections.
Some acknowledge errors can occur when the clock prescaler = 1 (BRP[5..0] = 0 in
CANBTR1 register) and the SMP bit is set (CANBTR3[0] = 1 in CANBTR3 register). That
can result in a reduction of the maximum length of the CAN bus.
Problem fix / workaround
If BRP[5..0]=0 use SMP=0.
If a Transmit Message Object (MOb) is enabled while the CAN bus is busy with an on going
message, the transmitter will wait for the 3-bit intermission before starting its transmission.
This is in full agreement with the CAN recommendation.
If the transmitter lost arbitration against another node, two conditions can occur:
- At least one receive MOb of the chip are programmed to accept the incoming message. In
- No receive MOb of the chip are programmed to accept the incoming message. In this case
Problem fix / workaround
Always have a receive MOb enabled ready to accept any incoming messages. Thanks to
the implementation of the CAN interface, a receive MOb must be enable at latest, before the
1
immediately after the 6th bit of the End of Frame field. This will leave in CAN2.0A mode a
minimum 19-bit time delay to respond to the end of message interrupt (RXOK) and re-
enable the receive MOb before the start of the DLC field of the next incoming message. This
st
this case, the transmitter will wait for the next 3-bit intermission to retry its transmission.
the transmitter will wait for a 4-bit intermission to retry its transmission. In this case, any
other CAN nodes ready to transmit after a 3-bit intermission will start transmit before the
chip transmitter, even if their messages have lower priority IDs.
bit of the DLC field. The receive MOb status register is written (RXOK if message OK)
Flash memory sections
From memory
space
D
B
B
A or C
T o me meo ry
space
B
D
B
A or C
M e m o r y
s p a c e
Application
0000h-2FFFh
0000h-37FFh
0000h-3BFFh
0000h-3DFFh
A
:
Bug comment
Allowed but should not be valid
Allowed but should not be valid
Not allowed but should be
Not allowed but should be
M e m o r y
s p a c e
Application
3000h-3FFFh
3800h-3FFFh
3C00h-3FFFh
3E00h-3FFFh
B
:
AT90CAN32/64/128
M e m o r y
s p a c e
Application
4000h-6FFFh
4000h-77FFh
4000h-7BFFh
4000h-7DFFh
C
:
M e m o r y
s p a c e
Bootloader
7000h-7FFFh
7800h-7FFFh
7C00h-7FFFh
7E00h-7FFFh
D
:
417
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