PIC16C73A-20E/SP Microchip Technology, PIC16C73A-20E/SP Datasheet - Page 54
![IC MCU OTP 4KX14 A/D PWM 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16C73A-20E/SP
Manufacturer Part Number
PIC16C73A-20E/SP
Description
IC MCU OTP 4KX14 A/D PWM 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C72-04SO.pdf
(289 pages)
4.PIC16C73A-20SP.pdf
(8 pages)
Specifications of PIC16C73A-20E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16C72-04SO PDF datasheet #3
- PIC16C73A-20SP PDF datasheet #4
- Current page: 54 of 289
- Download datasheet (3Mb)
PIC16C7X
5.7
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port when control bit PSPMODE
(TRISE<4>) is set. In slave mode it is asynchronously
readable and writable by the external world through RD
control input pin RE0/RD/AN5 and WR control input pin
RE1/WR/AN6.
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD/AN5 to be the RD input, RE1/
WR/AN6 to be the WR input and RE2/CS/AN7 to be the
CS (chip select) input. For this functionality, the corre-
sponding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set) and
the A/D port configuration bits PCFG2:PCFG0
(ADCON1<2:0>) must be set, which will configure pins
RE2:RE0 as digital I/O.
There are actually two 8-bit latches, one for data-out
(from the PIC16/17) and one for data input. The user
writes 8-bit data to PORTD data latch and reads data
from the port pin latch (note that they have the same
address). In this mode, the TRISD register is ignored,
since the microprocessor is controlling the direction of
data flow.
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), then the Input
Buffer Full status flag bit IBF (TRISE<7>) is set on the
Q4 clock cycle, following the next Q2 cycle, to signal
the write is complete (Figure 5-12). The interrupt flag bit
PSPIF (PIR1<7>) is also set on the same Q4 clock
cycle. IBF can only be cleared by reading the PORTD
input latch. The input Buffer Overflow status flag bit
IBOV (TRISE<5>) is set if a second write to the Parallel
Slave Port is attempted when the previous byte has not
been read out of the buffer.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full sta-
tus flag bit OBF (TRISE<6>) is cleared immediately
(Figure 5-13) indicating that the PORTD latch is waiting
to be read by the external bus. When either the CS or
RD pin becomes high (level triggered), the interrupt flag
bit PSPIF is set on the Q4 clock cycle, following the
next Q2 cycle, indicating that the read is complete.
OBF remains low until data is written to PORTD by the
user firmware.
When not in Parallel Slave Port mode, the IBF and OBF
bits are held clear. However, if flag bit IBOV was previ-
ously set, it must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
DS30390E-page 54
Parallel Slave Port
Applicable Devices
72 73 73A 74 74A 76 77
FIGURE 5-11: PORTD AND PORTE BLOCK
One bit of PORTD
Note: I/O pin has protection diodes to V
Data bus
Set interrupt flag
PSPIF (PIR1<7>)
WR
PORT
RD
PORT
Q
D
CK
DIAGRAM (PARALLEL
SLAVE PORT)
EN
EN
Q
D
1997 Microchip Technology Inc.
Chip Select
Read
Write
TTL
DD
TTL
TTL
TTL
and V
SS
RD
CS
WR
RDx
pin
.
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