AT90USB1287-AUR Atmel, AT90USB1287-AUR Datasheet - Page 222
AT90USB1287-AUR
Manufacturer Part Number
AT90USB1287-AUR
Description
MCU AVR 128K FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet
1.AT90USB646-MU.pdf
(461 pages)
Specifications of AT90USB1287-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT90USBx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525, ATAVRQTOUCHX
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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20.5.1
20.5.2
222
AT90USB64/128
SCL and SDA Pins
Bit Rate Generator Unit
Figure 20-9. Overview of the TWI Module
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a
slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike
suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR
pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as
explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need
for external ones.
This unit controls the period of SCL when operating in a Master mode. The SCL period is con-
trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status
Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the
CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note
that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock
period. The SCL frequency is generated according to the following equation:
Address Match Unit
Slew-rate
Arbitration detection
Control
START / STOP
Address Comparator
Address Register
Control
SCL
(TWAR)
Spike
Filter
Bus Interface Unit
Address/Data Shift
Spike Suppression
Register (TWDR)
Slew-rate
Control
SDA
Status Register
Ack
Spike
Filter
(TWSR)
State Machine and
Control Unit
Status control
Bit Rate Generator
Control Register
Bit Rate Register
Prescaler
(TWCR)
(TWBR)
7593K–AVR–11/09
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