PIC18F6525T-I/PT Microchip Technology, PIC18F6525T-I/PT Datasheet - Page 71
![IC PIC MCU FLASH 24KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F6525T-I/PT
Manufacturer Part Number
PIC18F6525T-I/PT
Description
IC PIC MCU FLASH 24KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F6525-IPT.pdf
(396 pages)
3.PIC18F6525-IPT.pdf
(8 pages)
4.PIC18F6525-IPT.pdf
(38 pages)
Specifications of PIC18F6525T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
MSSP, SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
2 x 8 bit
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F6525T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F6525-IPT PDF datasheet #2
- PIC18F6525-IPT PDF datasheet #3
- PIC18F6525-IPT PDF datasheet #4
- Current page: 71 of 396
- Download datasheet (8Mb)
EXAMPLE 5-3:
5.5.2
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
5.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. The WRERR bit is set when a
write operation is interrupted by a MCLR Reset or a
WDT Time-out Reset during normal operation. In these
situations, users can check the WRERR bit and rewrite
the location.
TABLE 5-2:
2005 Microchip Technology Inc.
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Legend:
Note 1:
PROGRAM_MEMORY
Name
Required
Sequence
x = unknown, u = unchanged, r = reserved, — = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
Bit 21 of the TBLPTRU allows access to device configuration bits.
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer High Byte (TBLPTR<7:0>)
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE
EEPROM Control Register 2 (not a physical register)
EEPGD
Bit 7
—
—
—
—
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
DECFSZ COUNTER_HI
BRA PROGRAM_LOOP
BCF
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
CFGS
CMIP
CMIE
CMIF
Bit 6
—
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
bit 21
Bit 5
—
—
—
—
(1)
Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
INT0IE
FREE
Bit 4
EEIP
EEIF
EEIE
PIC18F6525/6621/8525/8621
WRERR
BCLIP
BCLIF
BCLIE
RBIE
Bit 3
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
; write 55h
; write AAh
; start program (CPU stall)
; re-enable interrupts
; loop until done
; disable write to memory
TMR0IF
WREN
LVDIP
LVDIF
LVDIE
5.5.4
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 24.0 “Special Features of the
CPU” for more detail.
5.6
See Section 24.0 “Special Features of the CPU” for
details on code protection of Flash program memory.
Bit 2
TMR3IP
TMR3IF
TMR3IE
Flash Program Operation During
Code Protection
INT0IF
Bit 1
WR
PROTECTION AGAINST
SPURIOUS WRITES
CCP2IP
CCP2IF
CCP2IE
RBIF
Bit 0
RD
--00 0000
0000 0000
0000 0000
0000 0000
0000 000x
xx-0 x000
-1-1 1111
-0-0 0000
-0-0 0000
POR, BOR
Value on:
—
DS39612B-page 69
--00 0000
0000 0000
0000 0000
0000 0000
0000 000u
uu-0 u000
-1-1 1111
-0-0 0000
-0-0 0000
Value on
all other
Resets
—
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