PIC18F458-E/P Microchip Technology, PIC18F458-E/P Datasheet - Page 20
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PIC18F458-E/P
Manufacturer Part Number
PIC18F458-E/P
Description
IC MCU FLASH 16KX16 W/CAN 40 DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18LF242-ISO.pdf
(36 pages)
3.PIC18F248-ISO.pdf
(402 pages)
4.PIC18F248-ISO.pdf
(8 pages)
Specifications of PIC18F458-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
SPI, I2C, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM163011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F458-E/P
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
PIC18F458-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18FXX2/XX8
4.0
4.1
Code memory is accessed one byte at a time, via the
4-bit command, ‘1001’ (Table Read, post-increment).
The contents of memory pointed to by the Table Pointer
(TBLPTRU:TBLPTRH:TBLPTRL) are loaded into the
Table Latch and then serially output on SDATA.
TABLE 4-1:
FIGURE 4-1:
DS39576C-page 20
Step 1: Set Table Pointer.
Step 2: Read memory into Table Latch and then shift out on SDATA, LSb to MSb.
SCLK
SDATA
Command
0000
0000
0000
0000
0000
0000
1001
4-Bit
READING THE DEVICE
Read Code Memory, ID Locations,
and Configuration Bits
1
1
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
00 00
READ CODE MEMORY SEQUENCE
2
0
3
Data Payload
TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001)
0
4
1
P5
SDATA = Input
1
2
3
MOVLW Addr[21:16]
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
TBLRD *+
4
5
6
7
8
P6
The 4-bit command is shifted in LSb first. The Read is
executed during the next 8 clocks, then shifted out on
SDATA during the last 8 clocks, LSb to MSb. A delay of
P6 must be introduced after the falling edge of the 8th
SCLK of the operand to allow SDATA to transition from
an input to an output. During this time, SCLK must be
held low (see Table 4-1). This operation also
increments the Table Pointer pointer by one, pointing to
the next byte in code memory for the next read.
This technique will work to read any memory in the
000000h to 3FFFFFh address space, so it also applies
to the reading of the ID and configuration registers.
9
LSb
P14
10
1
Core Instruction
11
2
SDATA = Output
12
Shift Data Out
3
13
4
14
5
15
2010 Microchip Technology Inc.
6
16
MSb
P5A
Fetch Next 4-bit Command
1
SDATA = Input
n
2
n
3
n
4
n