PIC18F442-I/P Microchip Technology, PIC18F442-I/P Datasheet - Page 94

IC MCU FLASH 8KX16 EE A/D 40DIP

PIC18F442-I/P

Manufacturer Part Number
PIC18F442-I/P
Description
IC MCU FLASH 8KX16 EE A/D 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F442-I/P

Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
34
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
MSSP, SPI, I2C, PSP, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
34
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
 Details
Other names
PIC18F442I/P

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PIC18FXX2
TABLE 9-3:
TABLE 9-4:
DS39564C-page 92
PORTB
LATB
TRISB
INTCON
INTCON2
INTCON3
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
RB5/PGM
RB6/PGC
RB7/PGD
Legend: TTL = TTL input, ST = Schmitt Trigger input
Name
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Name
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: A device configuration bit selects which I/O pin the CCP2 pin is multiplexed on.
4: This buffer is a Schmitt Trigger input when configured as the CCP2 input.
5: Low Voltage ICSP Programming (LVP) is enabled by default, which disables the RB5 I/O function. LVP
(5)
(3)
LATB Data Output Register
PORTB Data Direction Register
must be disabled to enable RB5 as an I/O pin and allow maximum compatibility to the other 28-pin and
40-pin mid-range devices.
INT2IP
RBPU
GIEH
Bit 7
GIE/
RB7
PORTB FUNCTIONS
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
INTEDG0
INT1IP
PEIE/
Bit 6
GIEL
Bit#
RB6
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
INTEDG1
TMR0IE
Buffer
Bit 5
RB5
TTL
(1)
(1)
(1)
(4)
(2)
(2)
(2)
INTEDG2
INT0IE
INT2IE
Input/output pin or external interrupt input0.
Internal software programmable weak pull-up.
Input/output pin or external interrupt input1.
Internal software programmable weak pull-up.
Input/output pin or external interrupt input2.
Internal software programmable weak pull-up.
Input/output pin or Capture2 input/Compare2 output/PWM output when
CCP2MX configuration bit is enabled.
Internal software programmable weak pull-up.
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Low voltage ICSP enable pin.
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Serial programming clock.
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Serial programming data.
Bit 4
RB4
INT1IE
RBIE
Bit 3
RB3
TMR0IF
TMR0IP
Bit 2
RB2
INT0IF
INT2IF
Bit 1
RB1
Function
INT1IF
RBIP
Bit 0
RBIF
RB0
© 2006 Microchip Technology Inc.
xxxx xxxx
xxxx xxxx
1111 1111
0000 000x
1111 -1-1
11-0 0-00
POR, BOR
Value on
uuuu uuuu
uuuu uuuu
1111 1111
0000 000u
1111 -1-1
11-0 0-00
All Other
Value on
RESETS

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