PIC16C74A-10I/P Microchip Technology, PIC16C74A-10I/P Datasheet - Page 2

• Manufacturer Part Number: PIC16C74A-10I/P
• Description: IC MCU OTP 4KX14 A/D PWM 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C74A-10I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PIC16C74A
3. Module: CCP (Compare Mode)
4. Module: SSP (SPI Mode)
FIGURE 1:
DS80089A-page 2
The special event trigger of the Compare mode
may not occur if both of the following conditions
exist:
•
•
The interrupt for the compare event will still be
generated, but no special event trigger will occur.
Work around
Use the Interrupt Service Routine instead of using
the special event trigger to reset Timer1 (and start
an A/D conversion, if applicable).
When the SPI is using Timer2/2 as the clock
source, a shorter than expected SCK pulse may
occur on the first bit of the transmitted/received
data (Figure 1).
Work around
To avoid producing the short pulse, turn off Timer2
and clear the TMR2 register, load the SSPBUF
with the data to transmit, and then turn Timer2
back on. Refer to Example 1 for sample code.
CCP1
CCP2
Unit
SD0
SCK
An instruction, one cycle (T
Timer1/Compare register match has literal
data equal to the address of a CCP register
being used. Specific cases include:
An instruction in the same cycle as a
Timer1/Compare register match has an
MSb of ‘0’.
Write SSPBUF
SCK PULSE VARIATION
USING TIMER2/2
CCP1CON
CCP2C0N
bit0=1 bit1=0 bit2=1 . . . .
Register
CCPR1H
CCPR2H
CCPR1L
CCPR2L
CY
) prior to a
Literal Data
1Ch
1Dh
15h
16h
17h
1Bh
EXAMPLE 1:
5. Module: SSP Module (I
6. Module: Timer0
LOOP BTFSS SSPSTAT,BF
If the bus is active when the I
and the next 8 bits of data on the bus match the
address of the device, then the SSP module will
generate an Acknowledge pulse.
Work around
Before enabling the I
is not active.
The TMR0 register may increment when the WDT
postscaler is switched to the Timer0 prescaler. If
TMR0 = FFh, this will cause TMR0 to overflow
(setting T0IF).
Work around
Follow the following sequence:
a) Read the 8-bit TMR0 register into the
b) Clear the TMR0 register
c) Assign WDT postscaler to Timer0
d) Write W register to TMR0
BSF
GOTO
BCF
MOVF
MOVWF RXDATA
MOVF
BCF
CLR
MOVWF SSPBUF
BSF
W register
STATUS, RP0
LOOP
STATUS, RP0
SSPBUF, W
TXDATA, W
T2CON,
TMR2
T2CON,
SHORT SCK PULSE
AVOIDING THE INITIAL
 2001 Microchip Technology Inc.
TMR2ON ;Timer2 off
TMR2ON ;Timer2 on
2
C mode, ensure that the bus
2
;Bank 1
;Data received?
;(Xmit complete?)
;No
;Bank 0
;W = SSPBUF
;Save in user RAM
;W = TXDATA
;Clear Timer2
;Xmit New data
C™ mode)
2
C mode is enabled,