AT32UC3A3128S-ALUT Atmel, AT32UC3A3128S-ALUT Datasheet - Page 44
![IC MCU 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A3128S-ALUT
Manufacturer Part Number
AT32UC3A3128S-ALUT
Description
IC MCU 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.ATEVK1104.pdf
(90 pages)
Specifications of AT32UC3A3128S-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, I2S, JTAG, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
8.4.21
8.4.22
8.4.23
32072C–AVR32–2010/03
HSB Bus Performance Monitor
Multimedia Card Interface
Error Corrected Code Controller
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Allows performance monitoring of High Speed Bus master interfaces
The following is monitored
Automatic handling of event overflow
Compatible with Multimedia Card specification version 4.3
Compatible with SD Memory Card specification version 2.0
Compatible with SDIO specification version 1.1
Compatible with CE-ATA specification 1.1
Cards clock rate up to master clock divided by two
Boot Operation Mode support
High Speed mode support
Embedded power management to slow down clock rate when not used
Supports 2 Slots
Support for stream, block and multi-block data read and write
Supports connection to DMA Controller
Built in FIFO (from 16 to 256 bytes) with large memory aperture supporting incremental access
Support for CE-ATA completion cignal disable command
Protection against unexpected modification on-the-Fly of the configuration registers
Hardware Error Corrected Code Generation with two methods :
Supports NAND Flash and SmartMedia
8-bit data path for ECC-RS
Supports NAND Flash and SmartMedia
(specified by software)
ECC_H supports :
ECC_RS supports :
– Up to 4 masters can be monitored
– Peripheral Bus access to monitor registers
– Data transfer cycles
– Bus stall cycles
– Maximum access latency for a single transfer
– Each slot for either a MultiMediaCard bus (up to 30 cards) or an SD Memory Card
– Minimizes processor intervention for large buffer transfers
– Hamming code detection and correction by software (ECC-H)
– Reed-Solomon code detection by hardware, correction by hardware or software (ECC-RS)
– One bit correction per page of 512,1024,2048, or 4096 bytes
– One bit correction per sector of 512 bytes of data for a page size of 512, 1024, 2048, or 4096
– One bit correction per sector of 256 bytes of data for a page size of 512, 1024, 2048, or 4096
– 4 errors correction per sector of 512 bytes of data for a page size of 512, 1024, 2048, and
bytes
bytes
4096 bytes with 8-bit data path
™
™
devices with 8- or 16-bit data path for ECC-H, and with
with page sizes of 528, 1056, 2112, and 4224 bytes
AT32UC3A3/A4
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