PIC18LF6527-I/PT Microchip Technology, PIC18LF6527-I/PT Datasheet - Page 281
![IC PIC MCU FLASH 24KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18LF6527-I/PT
Manufacturer Part Number
PIC18LF6527-I/PT
Description
IC PIC MCU FLASH 24KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(446 pages)
3.PIC18F6527-IPT.pdf
(10 pages)
Specifications of PIC18LF6527-I/PT
Core Size
8-Bit
Program Memory Size
48KB (24K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3936 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
No. Of I/o's
54
Eeprom Memory Size
1024Byte
Ram Memory Size
3.84375KB
Cpu Speed
40MHz
No. Of Timers
5
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
54
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF6527-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18LF6527-I/PT
Manufacturer:
MIC
Quantity:
20 000
- Current page: 281 of 446
- Download datasheet (7Mb)
21.6
Figure 21-4 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
Figure 21-5 shows the operation of the A/D converter
after the GO/DONE bit has been set, the ACQT<2:0>
bits are set to ‘010’ and a 4 T
selected before the conversion starts.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
FIGURE 21-4:
FIGURE 21-5:
© 2008 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO/DONE bit
1
T
CY
Set GO/DONE bit
T
A/D Conversions
Holding capacitor is disconnected from analog input (typically 100 ns)
ACQT
Acquisition
Automatic
- T
2
Time
AD
Conversion starts
Cycles
T
AD
3
1 T
A/D CONVERSION T
A/D CONVERSION T
AD
b9
4
2 T
Conversion starts
(Holding capacitor is disconnected)
AD
b8
AD
1
3 T
acquisition time is
AD
b9
2
b7
4 T
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
AD
b8
3
b6
AD
AD
5 T
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> =
AD
b5
b7
4
6 T
T
AD
b4
5
b6
AD
7 T
Cycles
After the A/D conversion is completed or aborted, a
2 T
be started. After this wait, acquisition on the selected
channel is automatically started.
21.7
The discharge phase is used to initialize the value of
the capacitor array. The array is discharged before
every sample. This feature helps to optimize the unity-
gain amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
PIC18F8722 FAMILY
AD
b3
b5
Note:
6
AD
8
wait is required before the next acquisition can
T
AD
b4
b2
Discharge
7
9 T
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
AD
b3
8
b1
010
10
T
, T
AD
b0
b2
ACQ
9
ACQ
11
= 0)
T
= 4 T
AD
10
Discharge
b1
1
AD
b0
DS39646C-page 279
11
)
T
Discharge
AD
1
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