PIC17C43-16I/L Microchip Technology, PIC17C43-16I/L Datasheet - Page 120
![IC MCU OTP 4KX16 PWM 44PLCC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC17C43-16I/L
Manufacturer Part Number
PIC17C43-16I/L
Description
IC MCU OTP 4KX16 PWM 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C42A-16P.pdf
(241 pages)
3.PIC17C43-16P.pdf
(4 pages)
Specifications of PIC17C43-16I/L
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
33
Program Memory Size
8KB (4K x 16)
Program Memory Type
OTP
Ram Size
454 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
PIC17C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
454 B
Interface Type
SCI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
For Use With
AC164317 - MODULE SKT MPLAB PM3 44PLCCDVA17XL441 - DEVICE ADAPTER FOR PIC17C42A309-1007 - ADAPTER 44-PLCC ZIF TO 40-DIPAC174002 - MODULE SKT PROMATEII 44PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C43-16I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC17C4X
CPFSLT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
DS30412C-page 120
Before Instruction
After Instruction
Forced NOP
Decode
PC
W
If REG
PC
If REG
PC
Q1
Q1
register 'f'
Compare f with WREG,
skip if f < WREG
[ label ] CPFSLT
0
(f) – WREG),
skip if (f) < (WREG)
(unsigned comparison)
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
If the contents of 'f' < the contents of
WREG, then the fetched instruction is
discarded and an NOP is executed
instead making this a two-cycle instruc-
tion.
1
1 (2)
HERE
NLESS
LESS
None
Read
NOP
0011
Q2
Q2
=
=
<
=
f
=
255
Address (HERE)
?
WREG;
Address (LESS)
WREG;
Address (NLESS)
CPFSLT REG
:
:
0000
Execute
Execute
Q3
Q3
ffff
f
NOP
NOP
Q4
Q4
ffff
DAW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example1:
Example 2:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
WREG
REG1
C
DC
WREG
REG1
C
DC
WREG
REG1
C
DC
WREG
REG1
C
DC
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register 'f'
Decimal Adjust WREG Register
[ label ] DAW
0
s
If [WREG<3:0> >9] .OR. [DC = 1] then
else
If [WREG<7:4> >9] .OR. [C = 1] then
else
C
DAW adjusts the eight bit value in
WREG resulting from the earlier addi-
tion of two variables (each in packed
BCD format) and produces a correct
packed BCD result.
s = 0:
s = 1:
1
1
DAW
Read
0010
Q2
WREG<3:0> + 6
WREG<3:0>
WREG<7:4> + 6
WREG<7:4>
0xA5
??
0
0
0x05
0x05
1
0
0xCE
??
0
0
0x24
0x24
1
0
f
[0,1]
1996 Microchip Technology Inc.
255
REG1, 0
Result is placed in Data
memory location 'f' and
Result is placed in Data
memory location 'f'.
WREG.
111s
Execute
Q3
f,s
f<3:0>, s<3:0>;
f<7:4>, s<7:4>
ffff
f<3:0>, s<3:0>;
f<7:4>, s<7:4>
register 'f'
and other
specified
register
Write
Q4
ffff
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