ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet - Page 327

• Manufacturer Part Number: ATMEGA128A-AU
• Description: MCU 8BIT 128K ISP FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 8 Channel
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4784435

27.8
8151H–AVR–02/11
SPI Timing Characteristics
Table 27-5.
Notes:
See
Table 27-6.
Note:
Symbol
t
t
t
BVDV
OLDV
OHDZ
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Figure 27-7
1. t
2. t
1. In SPI Programming mode the minimum SCK high/low period is:
commands.
- 2 t
- 3 t
SS high to tri-state
WLRH
WLRH_CE
SCK to out high
SCK to SS high
SCK high/low
SS low to SCK
SCK high/low
Rise/Fall time
Rise/Fall time
SS low to out
Parameter
BS1 Valid to DATA valid
OE Low to DATA Valid
OE High to DATA Tri-stated
Parallel Programming Characteristics, V
SPI Timing Parameters
Description
CLCL
CLCL
SCK period
Out to SCK
SCK period
SCK to out
SCK to out
and
is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
Setup
Setup
Hold
Hold
for f
for f
is valid for the Chip Erase command.
Figure 27-8
CK
CK
< 12MHz
>12MHz
(1)
for details.
Master
Master
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
4 • t
2 • t
2 • t
Min
10
10
20
ck
ck
ck
CC
= 5V ±10% (Continued)
See
50% duty cycle
0.5 • t
Min
Table 19-4
Typ
0
3.6
10
10
10
10
15
15
10
sck
ATmega128A
Typ
Max
250
250
250
Max
1.6
Units
ns
ns
ns
ns
µs
ns
327