PIC18LF258-I/SO Microchip Technology, PIC18LF258-I/SO Datasheet - Page 279
![IC MCU CAN FLASH 16K LP 28-SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18LF258-I/SO
Manufacturer Part Number
PIC18LF258-I/SO
Description
IC MCU CAN FLASH 16K LP 28-SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18LF242-ISO.pdf
(36 pages)
4.PIC18F248-ISO.pdf
(402 pages)
5.PIC18F248-ISO.pdf
(8 pages)
Specifications of PIC18LF258-I/SO
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
22
Eeprom Memory Size
256Byte
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
SPI, I2C, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
22
Number Of Timers
4 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163011, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF258-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18LF242-ISO PDF datasheet #3
- PIC18F248-ISO PDF datasheet #4
- PIC18F248-ISO PDF datasheet #5
- Current page: 279 of 402
- Download datasheet (7Mb)
24.4.1
The user memory may be read to or written from any
location using the table read and table write instruc-
tions. The device ID may be read with table reads. The
Configuration registers may be read and written with
the table read and table write instructions.
In user mode, the CPn bits have no direct effect. CPn
bits inhibit external reads and writes. A block of user
memory may be protected from table writes if the
WRTn configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the
EBTRn bit set to ‘0’, a table read instruction that
executes from within that block is allowed to read. A
table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading ‘0’s. Figures 24-4 through 24-6
illustrate table write and table read protection.
FIGURE 24-4:
© 2006 Microchip Technology Inc.
TBLPTR = 000FFF
Results: All table writes disabled to Blockn whenever WRTn = 0.
Register Values
PROGRAM MEMORY
CODE PROTECTION
PC = 001FFE
PC = 004FFE
TABLE WRITE (WRTn) DISALLOWED
Program Memory
TBLWT *
TBLWT *
Note:
000000h
0001FFh
005FFFh
006000h
000200h
001FFFh
002000h
003FFFh
004000h
007FFFh
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
Configuration Bit Settings
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
PIC18FXX8
DS41159E-page 277
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