AT89C51RC2-3CSUM Atmel, AT89C51RC2-3CSUM Datasheet - Page 78

• Manufacturer Part Number: AT89C51RC2-3CSUM
• Description: IC 8051 MCU FLASH 32K 40DIP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RC2-3CSUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: SPI/UART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Cpu Family: AT89
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 60MHz
• Total Internal Ram Size: 1.25KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

WDT During Power-down
and Idle
78
AT89C51RB2/RC2
Table 60. WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
Reset Value = XXXX X000
In Power-down mode the oscillator stops, which means the WDT also stops. While in
Power-down mode the user does not need to service the WDT. There are two methods
of exiting Power-down mode: by a hardware reset or via a level activated external inter-
rupt which is enabled prior to entering Power-down mode. When Power-down is exited
with hardware reset, servicing the WDT should occur as it normally should whenever the
AT89C51RB2/RC2 is reset. Exiting Power-down with an interrupt is significantly differ-
ent. The interrupt is held low long enough for the oscillator to stabilize. When the
interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the
device while the interrupt pin is held low, the WDT is not started until the interrupt is
pulled high. It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of power-down,
it is better to reset the WDT just before entering power-down.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT89C51RB2/RC2 while in Idle mode, the user should always set up a timer that will
periodically exit Idle, service the WDT, and re-enter Idle mode.
Number
Bit
7
-
7
6
5
4
3
2
1
0
Mnemonic Description
Bit
S2
S1
S0
6
-
-
-
-
-
-
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
WDT Time-out Select Bit 2
WDT Time-out Select Bit 1
WDT Time-out Select Bit 0
S2
0
0
0
0
1
1
1
1
5
-
S1
0
0
1
1
0
0
1
1
S0Selected Time-out
0(2
1(2
0 (2
1(2
0(2
1 (2
0(2
1 (2
14
15
17
18
20
16
19
21
4
-
- 1) machine cycles, 16. 3 ms @ F
- 1) machine cycles, 32.7 ms @ F
- 1) machine cycles, 131 ms @ F
- 1) machine cycles, 262 ms @ F
- 1) machine cycles, 1.05 s @ F
- 1) machine cycles, 65. 5 ms @ F
- 1) machine cycles, 542 ms @ F
- 1) machine cycles, 2.09 s @ F
3
-
S2
2
OSCA
OSCA
OSCA
OSCA
OSCA
OSCA
OSCA
OSCA
= 12 MHz
= 12 MHz
= 12 MHz
= 12 MHz
S1
= 12 MHz
= 12 MHz
1
= 12 MHz
= 12 MHz
4180E–8051–10/06
S0
0