AT91M55800A-33CJ Atmel, AT91M55800A-33CJ Datasheet - Page 249

• Manufacturer Part Number: AT91M55800A-33CJ
• Description: IC ARM MCU 16BIT 176BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M55800A-33CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 58
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91EB55
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• Cpu Family: AT91
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 58
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: BGA
• For Use With: AT91EB55 - KIT EVAL FOR ARM AT91M55800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

27.3
27.4
27.5
1745F–ATARM–06-Sep-07
APMC: Unpredictable Result in APMC State Machine on Switch from Oscillator to PLL
APMC: Clock Switching with the Prescaler in the APMC is not Permitted
SPI: Initializing SPI in Master Mode May Cause a Mode Fault Detection
If the first two conditions are not met during write accesses, the NWE signal is not affected by
the NWAIT assertion. The following example illustrates the number of standard wait states.
NWAIT is not asserted during the first cycle, but is asserted at the second and last cycle of the
standard access. The access is correctly delayed as the NCS line rises accordingly to the
NWAIT assertion. However, the NWE signal waveform is unchanged, and rises too early.
Figure 27-4. Description of the Number of Standard Wait States
An automatic switch from the main oscillator output (CSS = 1) may cause an unpredictable
result in the APMC state machine. The automatic PLL to PLL transition is also effected by this
problem.
The user must either wait for the PLL lock flag to be set in the APMC status register or switch to
an intermediate 32 kHz oscillator output (CSS = 0).
Switching from the selected clock (PRES = 0) to the selected clock divided by 4 (PRES = 2), 8
(PRES = 3) or 64 (PRES = 6) may lead to unpredictable results.
First, the user should switch to any other value (PRES = 1, 4 or 5) and wait for the actual switch
to perform (at least 64 cycles of the selected clock). Then, the user can write the final prescaler
value.
In order to prevent this error, the user must pull up the PA26/NPCS0/NSS pin to the V
supply.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
MCKI
NWAIT
NCS
NWE
Access Length = One Wait State + Assertion of the NWAIT for One More Cycle
EBI
5
AT91M5880A
Erroneous NWE Rising
DDIO
power
249