AT89C51AC3-SLSUM Atmel, AT89C51AC3-SLSUM Datasheet - Page 47

• Manufacturer Part Number: AT89C51AC3-SLSUM
• Description: IC 8051 MCU FLASH 64K 44PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51AC3-SLSUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2304 B
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 44PLCC
• Device Core: 8051
• Family Name: 89C
• Maximum Speed: 60 MHz
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4383D–8051–02/08
order. The page address of the last address loaded in the column latches will be used
for the whole page.
When programming is launched, an automatic erase of the locations loaded in the col-
umn latches is first performed, then programming is effectively done. Thus no page or
block erase is needed and only the loaded data are programmed in the corresponding
page
Notes:
The following procedure is used to load the column latches and is summarized in
Figure 25:
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Save and Disable interrupt and map the column latch space by setting FPS bit.
Load the DPTR with the address to load.
Load Accumulator register with the data to load.
Execute the MOVX @DPTR, A instruction.
If needed loop the three last instructions until the page is completely loaded.
unmap the column latch.
Restore Interrupt
1. : If no bytes are written in the column latches the SEQERR bit in the FSTA register
2. When a flash write sequence is in progress (FBUSY is set) a write sequence to the
3. MOVX @DPTR, A instruction must be used to load the column latches. Never use
4. When a programming sequence is launched, Flash bytes corresponding to activated
will be set.
column latches will be ignored and the content of the column latches at the time of
the launch write sequence will be preserved.
MOVX @Ri, A instructions.
bytes in the column latches are first erased then the bytes in the column latches are
copied into the Flash bytes. Flash bytes corresponding to bytes in the column latches
not activated (not loaded during the load column latches sequence) will not be erased
and written.
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