ATSAM3U2CA-AU Atmel, ATSAM3U2CA-AU Datasheet - Page 470
ATSAM3U2CA-AU
Manufacturer Part Number
ATSAM3U2CA-AU
Description
IC MCU 32BIT 128KB FLASH 100LQFP
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U2CA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
57
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b, 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Controller Family/series
SAM3U
No. Of I/o's
57
Ram Memory Size
36KB
Cpu Speed
96MHz
No. Of Timers
3
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
36 KB
Interface Type
3xUSART, TWI, 4xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
57
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3U2CA-AU
Manufacturer:
INFINEON
Quantity:
12 000
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28.12 Clock Switching Details
28.12.1
470
SAM3U Series
Master Clock Switching Timings
Table 28-1
from one selected clock to another one. This is in the event that the prescaler is de-activated.
When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock
has to be added.
Table 28-1.
Notes:
Table 28-2.
To
Main Clock
SLCK
PLL Clock
To
PLLA Clock
UPLL Clock
1. PLL designates either the PLLA or the UPLL Clock.
2. PLLCOUNT designates either PLLACOUNT or UPLLCOUNT.
and
From
Clock Switching Timings (Worst Case)
Clock Switching Timings between Two PLLs (Worst Case)
From
Table 28-2
PLLCOUNT x SLCK +
0.5 x Main Clock +
0.5 x Main Clock +
2.5 x PLLx Clock
Main Clock
give the worst case timings required for the Master Clock to switch
4.5 x SLCK
4 x SLCK +
PLLACOUNT x SLCK
2.5 x PLLA Clock +
3 x UPLL Clock +
1.5 x UPLL Clock
–
PLLA Clock
4 x SLCK +
4 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
2.5 x Main Clock
4 x SLCK +
5 x SLCK +
SLCK
–
UPLLCOUNT x SLCK
2.5 x UPLL Clock +
3 x PLLA Clock +
1.5 x PLLA Clock
UPLL Clock
4 x SLCK +
4 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
3 x PLL Clock +
3 x PLL Clock +
6430D–ATARM–25-Mar-11
1 x Main Clock
4 x SLCK +
4 x SLCK +
PLL Clock
5 x SLCK
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