AT32UC3A1256-AUT Atmel, AT32UC3A1256-AUT Datasheet - Page 70
AT32UC3A1256-AUT
Manufacturer Part Number
AT32UC3A1256-AUT
Description
IC MCU AVR32 256KB FLASH 100TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A1256-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Package
100TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
69
Interface Type
Ethernet/I2S/JTAG/SPI/TWI/USART
Number Of Timers
3
Controller Family/series
AT32UC3A
No. Of I/o's
69
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
AT32UC3x
Core
AVR32
Data Ram Size
64 KB
Maximum Clock Frequency
66 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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13.6.3
Name:
Access Type:
•
Table 13-5.
32058J–AVR32–04/11
MASK: Clock Mask
Bit
10
11
12
13
0
1
2
3
4
5
6
7
8
9
31
23
15
7
If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current
power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is
shown in
Clock Mask
CPUMASK
Maskable module clocks in AT32UC3A.
OCD
Table
-
-
-
-
-
-
-
-
-
-
-
-
-
30
22
14
6
CPU/HSB/PBA/PBBMASK
Read/Write
13-5.
29
21
13
5
HSBMASK
PBA bridge
PBB bridge
FLASHC
MACB
PDCA
USBB
EBI
-
-
-
-
-
-
-
28
20
12
4
MASK[31:24]
MASK[23:16]
MASK[15:8]
MASK[7:0]
PM/RTC/EIC
PBAMASK
USART0
USART1
USART2
USART3
PDCA
GPIO
PWM
INTC
SPI0
SPI1
ADC
SSC
TWI
27
19
11
3
26
18
10
2
PBBMASK
HMATRIX
SDRAMC
FLASHC
MACB
USBB
SMC
-
-
-
-
-
-
-
-
25
17
9
1
AT32UC3A
24
16
8
0
70
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