ATSAM3U2CA-CU Atmel, ATSAM3U2CA-CU Datasheet - Page 905
ATSAM3U2CA-CU
Manufacturer Part Number
ATSAM3U2CA-CU
Description
IC MCU 32BIT 128KB FLSH 100TFBGA
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U2CA-CU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
57
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b, 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
36 KB
Interface Type
3xUSART, TWI, 4xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
57
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3U2CA-CU
Manufacturer:
PERICOM
Quantity:
3 186
Part Number:
ATSAM3U2CA-CU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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38.7.9
Name:
Address:
Access:
This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in
page
• SYNCx: Synchronous Channel x
0 = Channel x is not a synchronous channel.
1 = Channel x is a synchronous channel.
• UPDM: Synchronous Channels Update Mode
Notes:
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Value
0
1
2
3
928.
31
23
15
–
–
7
–
1. The update occurs at the beginning of the next PWM period, when the UPDULOCK bit in
2. The update occurs when the Update Period is elapsed.
PWM Sync Channels Mode Register
Control Register”
PWM_SCM
0x4008C020
Read-write
MODE0
MODE1
MODE2
Name
–
PTRCS
30
22
14
–
–
6
–
is set.
Manual write of double buffer registers and manual update of synchronous channels
Manual write of double buffer registers and automatic update of synchronous channels
Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous
channels
Reserved
29
21
13
–
–
5
–
(2)
PTRM
28
20
12
–
–
4
–
SYNC3
27
19
11
–
–
–
3
Description
SYNC2
“PWM Write Protect Status Register” on
26
18
10
–
–
–
2
“PWM Sync Channels Update
SAM3U Series
SAM3U Series
SYNC1
25
17
–
9
–
1
UPDM
(1)
(2)
SYNC0
24
16
–
8
–
0
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