AT32UC3A1512-AUT Atmel, AT32UC3A1512-AUT Datasheet - Page 518

• Manufacturer Part Number: AT32UC3A1512-AUT
• Description: IC MCU AVR32 512KB FLASH 100TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A1512-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire/RS-485/SPI/USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
• Minimum Operating Temperature: - 40 C
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 30-19. Abort Algorithm
30.7.2.13
30.7.2.13.1 Overview
32058J–AVR32–04/11
Management of OUT Endpoints
OUT packets are sent by the host. All the data can be read by the firmware which acknowledges
or not the bank when it is empty.
The endpoint must be configured first.
The RXOUTI bit is set by hardware at the same time as FIFOCON when the current bank is full.
This triggers an EPXINT interrupt if RXOUTE = 1.
RXOUTI shall be cleared by software (by setting the RXOUTIC bit) to acknowledge the interrupt,
what has no effect on the endpoint FIFO.
The firmware then reads from the FIFO and clears the FIFOCON bit to free the bank. If the OUT
endpoint is composed of multiple banks, this also switches to the next bank. The RXOUTI and
FIFOCON bits are updated by hardware in accordance with the status of the next bank.
RXOUTI shall always be cleared before clearing FIFOCON.
The RWALL bit is set by hardware when the current bank is not empty, i.e. the software can read
further data from the FIFO.
EPRSTX = 1
TXINEC = 1
Abort Done
NBUSYBK
Endpoint
== 0?
Abort
Yes
No
Yes
KILLBKS = 1
KILLBK
== 1?
No
Disable the TXINI interrupt.
Abort is based on the fact
that no bank is busy, i.e. that
nothing has to be sent.
Kill the last written bank.
Wait for the end of the
procedure.
AT32UC3A
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