DSPIC30F6011T-20E/PF Microchip Technology, DSPIC30F6011T-20E/PF Datasheet - Page 3
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DSPIC30F6011T-20E/PF
Manufacturer Part Number
DSPIC30F6011T-20E/PF
Description
IC DSPIC MCU/DSP 132K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F6014-20IPF.pdf
(228 pages)
3.DSPIC30F6014-20IPF.pdf
(22 pages)
4.DSPIC30F6014-20IPF.pdf
(28 pages)
Specifications of DSPIC30F6011T-20E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
132KB (44K x 24)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TQFP, 64-VQFP
For Use With
XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F6011T20EP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6011T-20E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
TABLE 2:
© 2010 Microchip Technology Inc.
Operations
Note 1:
Controller
Interrupt
Memory
Memory
Module
Sleep
Timer
Flash
Flash
Mode
I
CAN
CPU
PSV
CAN
2
PLL
PLL
PLL
I/O
I
I
I
I
C™
2
2
2
2
C
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
Bus Collision
RX Filters 3,
Sleep Mode
Slave Mode
I
Multiplexed
Lock Status
Addressing
Addressing
Addressing
Operations
Regulation
DD
Protection
on SFRs
4x Mode
8x Mode
Feature
with IC1
Port Pin
SILICON ISSUE SUMMARY (CONTINUED)
4 and 5
Voltage
10-bit
10-bit
10-bit
Read
Code
Current
—
—
bit
—
Number
Item
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
Read operations performed on CAN module Special Function
Registers (SFRs) may yield incorrect results at operation over
20 MIPS.
This release of silicon exhibits a current draw (I
approximately 370 mA during a Row Erase operation performed
on program Flash memory.
For this release of silicon, applications operating off 5 volts V
30 MIPS should ensure that the V
Addresses in the range 0x6000 through 0xFFFF may not be
code-protected for this revision of dsPIC30F6011 and
dsPIC30F6013 silicon.
The 4x PLL mode of operation may not function correctly for
certain input frequencies.
An interrupt occurring immediately after modifying the CPU IPL,
interrupt IPL, interrupt enable or interrupt flag may cause an
address error trap.
If 8x PLL mode is used, the input frequency range is 5 MHz-10 MHz
instead of 4 MHz-10 MHz.
Execution of the Sleep instruction (PWRSAV #0) may cause
incorrect program operation after the device wakes up from
Sleep. The current consumption during Sleep may also increase
beyond the specifications listed in the device data sheet.
The I
I
The port I/O pin multiplexed with the Input Capture 1 (IC1)
function cannot be used as a digital input pin when the UART
auto-baud feature is enabled.
When the I
the same address bits (A10 and A9) as other I
A10 and A9 bits may not work as expected.
Clock switching prevents the device from waking up from Sleep.
The PLL LOCK Status bit (OSCCON<5>) can occasionally get
cleared and generate an oscillator failure trap even when the
PLL is still locked and functioning correctly.
An address error trap occurs in certain addressing modes when
accessing the first four bytes of any PSV page.
The 10-bit slave does not set the RBF flag or load the I2CxRCV
register, on address match if the Least Significant bits (LSbs) of
the address are the same as the 7-bit reserved addresses.
When the I
address of 0x102, the I2CxRCV register content for the lower
address byte is 0x01 rather than 0x02.
When the I
generates a glitch on the SDA and SCL pins, causing a false
communication start in a single-master configuration or a bus
collision in a multi-master configuration.
CAN Receive filters 3, 4 and 5 may not work for a given
combination of instruction cycle speed and CAN bit time quanta.
2
C slave.
2
C module loses incoming data bytes when operating as an
2
2
2
C module is configured for 10-bit addressing using
C module is configured as a 10-bit slave with an
C module is enabled, the dsPIC
dsPIC30F6011/6012/6013/6014
Issue Summary
DD
remains within 5% of 5 volts.
®
DSC device
2
DD
C devices, the
) of
DD
at
DS80456D-page 3
Revisions
A3 B1 B2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X