AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 29

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

9.2
9.3
9.4
Figure 9-2.
6249HS–ATARM–27-Jul-09
Reset Controller
Shutdown Controller
Clock Generator
Clock Generator Block Diagram
• Based on two Power-on-Reset cells
• Status of the last reset
• Controls the internal resets and the NRST pin output
• Shutdown and Wake-up logic
• Embeds the low-power 32768 Hz Slow Clock Oscillator
• Embeds the Main Oscillator
• Embeds 2 PLLs
– One on VDDBU and one on VDDCORE
– Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software
– Allows shaping a reset signal for the external devices
– Software programmable assertion of the SHDN pin (SHDN is push-pull)
– Deassertion programmable on a WKUP pin level change or on alarm
– Provides the permanent Slow Clock SLCK to the system
– Oscillator bypass feature
– Supports 3 to 20 MHz crystals
– Output 80 to 240 MHz clocks
– Integrates an input divider to increase output accuracy
– 1 MHz Minimum input frequency
reset, user reset or watchdog reset
XOUT32
PLLRCA
PLLRCB
XIN32
XOUT
XIN
Clock Generator
Management
Slow Clock
Controller
Oscillator
Oscillator
Status
PLL and
Divider A
PLL and
Divider B
Power
Main
Control
AT91SAM9263 Preliminary
Slow Clock
SLCK
Main Clock
MAINCK
PLLA Clock
PLLACK
PLLB Clock
PLLBCK
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